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COM20019I Datasheet(PDF) 51 Page - SMSC Corporation |
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COM20019I Datasheet(HTML) 51 Page - SMSC Corporation |
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51 / 65 page  Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM SMSC COM20019I Page 51 Rev. 09-25-07 DATASHEET Figure 8.4 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE AD0-AD2, VALID nCS t1 t3 ALE VALID DATA t2, t6 t5 t4 t7 D3-D7 Note 2 t8** nWR t9 t10 nRD t13 t11 t12 t8 Note 3 Parameter min max units t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 20 10 10 10 15 10 4TARB * 20 20 20 20 20 nS nS nS nS nS nS nS nS nS nS nS nS nS Address Setup to ALE Low Address Hold from ALE Low nCS Setup to ALE Low nCS Hold from ALE Low ALE Low to nDS Low Valid Data Setup to nDS High Data Hold from nDS High 30 ALE High Width ALE Low Width nWR Low Width nWR High Width nRD to nWR Low Cycle Time (nWR to Next )** TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 * TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. Same as the XTAL1 period. The Microcontroller typically accesses the COM20019 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20019 cycles. Note 1: Any cycle occurring after a write to Address Pointer Low Register requires a minimum of 4TARB from the trailing edge of nWR to the leading edge of the next nWR. Note 2: ** Write cycle for Address Pointer Low Register occurring after a write to Data Register requires a minimum of 5TARB from the trailing edge of nWR to the leading edge of the next nWR. Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5TARB from the trailing edge of nRD to the leading edge of nWR. |
Similar Part No. - COM20019I_07 |
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Similar Description - COM20019I_07 |
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