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ADS5545 Datasheet(PDF) 23 Page - Texas Instruments |
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ADS5545 Datasheet(HTML) 23 Page - Texas Instruments |
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www.ti.com ADS5517 SLWS203 – DECEMBER 2007 PIN ASSIGNMENTS – LVDS Mode (continued) PIN PIN NUMBER PIN NAME DESCRIPTION TYPE NUMBER OF PINS This pin functions as serial interface clock input when RESET is low. It functions as LOW SPEED control pin when RESET is tied high. Tie SCLK to SCLK I 29 1 LOW for Fs > 50 MSPS and SCLK to HIGH for Fs ≤ 50 MSPS. See Table 3. The pin has an internal 100-k Ω pull-down resistor. This pin functions as serial interface data input when RESET is low. It functions as STANDBY control pin when RESET is tied high. SDATA I 28 1 See Table 4 for detailed information. The pin has an internal 100 k Ω pull-down resistor. This pin functions as serial interface enable input when RESET is low. It functions as CLKOUT edge programmability when RESET is tied high. See Table 5 for SEN I 27 1 detailed information. The pin has an internal 100-k Ω pull-up resistor to DRVDD. Output buffer enable input, active high. The pin has an internal 100-k Ω pull-up OE I 7 1 resistor to DRVDD. Data Format Select input. This pin sets the DATA FORMAT (Twos complement or DFS Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed I 6 1 information. Mode select input. This pin selects the Internal or External reference mode. See MODE I 23 1 Table 7 for detailed information. CLKOUTP Differential output clock, true O 5 1 CLKOUTM Differential output clock, complement O 4 1 LOW_D0_P Differential output data LOW and D0 multiplexed, true O 38 1 LOW_D0_M Differential output data LOW and D0 multiplexed, complement O 37 1 D1_D2_P Differential output data D1 and D2 multiplexed, true O 40 1 D1_D2_M Differential output data D1 and D2 multiplexed, complement O 39 1 D3_D4_P Differential output data D3 and D4 multiplexed, true O 42 1 D3_D4_M Differential output data D3 and D4 multiplexed, complement O 41 1 D5_D6_P Differential output data D5 and D6 multiplexed, true O 44 1 D5_D6_M Differential output data D5 and D6 multiplexed, complement O 43 1 D7_D8_P Differential output data D7 and D8 multiplexed, true O 46 1 D7_D8_M Differential output data D7 and D8 multiplexed, complement O 45 1 D9_D10_P Differential output data D9 and D10 multiplexed, true O 48 1 D9_D10_M Differential output data D9 and D10 multiplexed, complement O 47 1 OVR Out-of-range indicator, CMOS level signal O 3 1 DRVDD Digital and output buffer supply I 2, 35 2 DRGND Digital and output buffer ground I 1, 36 2 31, 32, 33, NC Do not connect 4 34 Connect the pad to the ground plane. See Board Design Considerations in PAD 0 1 application information section. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Link(s): ADS5517 |
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