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ADS5545 Datasheet(PDF) 13 Page - Texas Instruments

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Part No. ADS5545
Description  11-BIT, 200 MSPS ADC
Download  54 Pages
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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ADS5545 Datasheet(HTML) 13 Page - Texas Instruments

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DESCRIPTION OF PARALLEL PINS
SERIAL INTERFACE
ADS5517
SLWS203 – DECEMBER 2007
Table 3. SCLK Control Pin
SCLK (Pin 29)
DESCRIPTION
0
LOW SPEED mode Disabled - Use for sampling frequencies above 50 MSPS.
DRVDD
LOW SPEED mode Enabled - Use for sampling frequencies below 50 MSPS.
Table 4. SDATA Control Pin
SDATA (Pin 28)
DESCRIPTION
0
Normal operation (Default)
DRVDD
STANDBY. This is a global power down, where ADC, internal references and the output buffers are powered down.
Table 5. SEN Control Pin
SEN (Pin 27)
DESCRIPTION
0
CMOS mode: CLKOUT edge later by (3/12)Ts (1); LVDS mode: CLKOUT edge aligned with data transition
(1/3)DRVDD
CMOS mode: CLKOUT edge later by (2/12)Ts ; LVDS mode: CLKOUT edge aligned with data transition
(2/3)DRVDD
CMOS mode: CLKOUT edge later by (1/12)Ts ; LVDS mode: CLKOUT edge earlier by (1/12)Ts
DRVDD
Default CLKOUT position
(1)
Ts = 1/Sampling Frequency
Table 6. DFS Control Pin
DFS (Pin 6)
DESCRIPTION
0
2's complement data and DDR LVDS output (Default)
(1/3)DRVDD
2's complement data and parallel CMOS output
(2/3)DRVDD
Offset binary data and parallel CMOS output
DRVDD
Offset binary data and DDR LVDS output
Table 7. MODE Control Pin
MODE (Pin 23)
DESCRIPTION
0
Internal reference
(1/3)AVDD
External reference
(2/3)AVDD
External reference
AVDD
Internal reference
The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device
power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET
(of width greater than 10 ns).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in
multiples of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits form the register data. The interface can work
with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK duty
cycle.
Copyright © 2007, Texas Instruments Incorporated
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Product Folder Link(s): ADS5517


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