Electronic Components Datasheet Search |
|
ADS5545 Datasheet(PDF) 8 Page - Texas Instruments |
|
|
ADS5545 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 54 page www.ti.com ADS5517 SLWS203 – DECEMBER 2007 TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued) For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data sheet. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input clock rising edge zero-cross to output tPDI Clock propagation delay(7) 3.7 4.4 5.1 ns clock rising edge zero-cross Duty cycle of differential clock, LVDS bit clock duty cycle (CLKOUTP-CLKOUTM) 45% 50% 55% 80 ≤ Fs ≤ 200 MSPS Rise time measured from –50 mV to 50 tr , Data rise time, mV 50 100 200 ps tf Data fall time Fall time measured from 50 mV to –50 mV 1 ≤ Fs ≤ 200 MSPS Rise time measured from –50 mV to 50 tCLKRISE, Output clock rise time, mV 50 100 200 ps tCLKFALL Output clock fall time Fall time measured from 50 mV to –50 mV 1 ≤ Fs ≤ 200 MSPS Output clock jitter Cycle-to-cycle jitter 120 ps pp Output enable (OE) to valid data Time to valid data after OE becomes tOE 1 µs delay active PARALLEL CMOS MODE Data valid(8) to 50% of CLKOUT rising ns tsu Data setup time (5) 1.8 2.6 edge 50% of CLKOUT rising edge to data th Data hold time (5) 0.4 0.8 ns becoming invalid(8) Input clock rising edge zero-cross to 50% tPDI Clock propagation delay(7) 2.6 3.4 4.2 ns of CLKOUT rising edge Duty cycle of output clock (CLKOUT) Output clock duty cycle 45% 80 ≤ Fs ≤ 200 MSPS Rise time measured from 20% to 80% of DRVDD tr , Data rise time, Fall time measured from 80% to 20% of 0.8 1.5 2.0 ns tf Data fall time DRVDD 1 ≤ Fs ≤ 200 MSPS Rise time measured from 20% to 80% of DRVDD tCLKRISE, Output clock rise time, Fall time measured from 80% to 20% of 0.4 0.8 1.2 ns tCLKFALL Output clock fall time DRVDD 1 ≤ Fs ≤ 200 MSPS Output enable (OE) to valid data Time to valid data after OE becomes tOE 50 ns delay active (7) To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay (tD) to get the desired setup and hold times. Use either of these equations to calculate tD: Desired setup time = tD - (tPDI - tsu ) Desired hold time = (tPDI + th ) - tD (8) Data valid refers to logic high of 2 V and logic low of 0.8 V 8 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS5517 |
Similar Part No. - ADS5545 |
|
Similar Description - ADS5545 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |