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ADS5545 Datasheet(PDF) 36 Page - Texas Instruments

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Part No. ADS5545
Description  11-BIT, 200 MSPS ADC
Download  54 Pages
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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ADS5545 Datasheet(HTML) 36 Page - Texas Instruments

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CLKP
CLKM
DifferentialSine-Wave
orPECL orLVDS
ClockInput
0.1 F
m
0.1 F
m
CLKP
CLKM
CMOSClockInput
0.1 F
m
0.1 F
m
Clock Buffer Gain
ADS5517
SLWS203 – DECEMBER 2007
For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to
common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with
0.1-
µF capacitors, as shown in Figure 40.
Figure 40. Differential Clock Driving Circuit
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin 11) connected to ground with
a 0.1-
µF capacitor, as shown in Figure 41.
Figure 41. Single-Ended Clock Driving Circuit
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, the use a clock source with low jitter is recommended. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input. Figure 25 shows the performance variation of the ADC versus clock duty cycle
When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is
increased. Therefore, using a large amplitude clock is recommended. In addition, the clock buffer has a
programmable gain option to amplify the input clock. The clock buffer gain can be set by programming the
register bits <CLKIN GAIN> (Table 14). The clock buffer gain decreases monotonically from Gain 4 to Gain 0
settings.
36
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS5517


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