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M24512-W Datasheet(PDF) 6 Page - STMicroelectronics

Part No. M24512-W
Description  512 Kbit and 256 Kbit serial I²C bus EEPROM with three Chip Enable lines
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M24512-W Datasheet(HTML) 6 Page - STMicroelectronics

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Description
M24512-x, M24256-Bx
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1
Description
The M24512-W, M24512-R, M24512-HR, M24256-BW, M24256-BR and M24256-BHR
devices are I2C-compatible electrically erasable programmable memories (EEPROM). They
are organized as 64 Kb × 8 bits and 32 Kb × 8 bits, respectively.
I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The
devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C
bus definition.
The device behaves as a slave in the I2C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in Table 2), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Figure 1.
Logic diagram
Table 1.
Signal names
Signal name
Function
Direction
E0, E1, E2
Chip Enable
Inputs
SDA
Serial Data
I/O
SCL
Serial Clock
Input
WC
Write Control
Input
VCC
Supply voltage
VSS
Ground
AI02275d
SDA
VCC
M24512-W
M24512-R
M24512-HR
M24256-BW
M24256-BR
M24256-BHR
WC
SCL
VSS
3
E0-E2


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