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MK50H27Q Datasheet(PDF) 1 Page - STMicroelectronics |
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MK50H27Q Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 56 page  MK50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements Pin-for-pin and architecturally compatible with MK50H25 (X.25/LAPD), MK50H29 (SDLC), and MK50H28(Frame Relay). System clock rates up to 33 MHz (MK50H27 - 33), or 25 MHz (MK50H27 - 25). Data rate up to 4 Mbps continuous for SS7 protocol processing, 20 Mbps for transparent HDLC mode, or up to 51 Mbps bursted (gapped data clocks, non-continuous data). On chip DMA control with programmable burst length. DMA transfer rate of up to 13.3 Mbytes/sec us- ing optional 5 SYSCLK DMA cycle (150 nS) at 33 MHz SYSCLK. Buffer Management includes: - Initialization Block - Separate Receive and Transmit Rings - Variable Descriptor Ring and Window Sizes. Selectable BEC or PCR retransmission meth- ods, including forced retransmission for PCR. Handles all 7 SS7 Timers, plus the additional Signal Unit interval timers for Japanese SS7. Handles all SS7 frame formatting: - Zero bit insert and delete - FCS generation and detection - Frame delimiting with flags Programmable minimum Signal Unit spacing (number of flags between SU’s) Handles all sequencing and link control. Selectable FCS of 16 or 32 bits. Testing Facilities: - Internal Loopback - Silent Loopback - Optional Internal Data Clock Generation - Self Test. Programmable for full or half duplex operation Programmable Watchdog Timers for RCLK and TCLK (to detect absence of data clocks) Available in 52 pin PLCC, 84 pin PLCC(for use with external ROM), or 48 pin DIP packages. SECTION 2 - INTRODUCTION The SGS - Thomson SS7 Signalling Link Control- ler (MK50H27) is a VLSI semiconductor device which provides a complete level 2 data communi- cation control conforming to the CCITT, ANSI, BELLCORE, and AT&T versions of SS7, as well as options to allow conformance to TTC JT-Q703 (Japanese SS7). This includes signal unit format- ting, transparency (so-called ”bit-stuffing”), error recovery by two types of retransmission, error monitoring, sequence number control, link status control, and fill in signal unit generation. One of the outstanding features of the MK50H27 is its buffer management which includes on-chip DMA. This feature allows users to handle multi- ple MSU’s of receive and transmit data at a time. (A conventional data link control chip plus a sepa- rate DMA chip would handle data for only a single block at a time.) The MK50H27 will move multiple blocks of receive and transmit data directly into September 1997 DIP48 PLCC 52 1/56 |
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