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MK50H28 Datasheet(PDF) 4 Page - STMicroelectronics |
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MK50H28 Datasheet(HTML) 4 Page - STMicroelectronics |
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4 / 64 page  SIGNAL NAME PIN(S) TYPE DESCRIPTION DAL<15:00> 2-9 40-47 [2-10 44-51] IO/3S The time multiplexed Data/Address bus. During the address portion of a memory transfer, DAL<15:00> contains the lower 16 bits of the memory address. During the data portion of a memory transfer, DAL<15:00> contains the read or write data, depending on the type of transfer. READ 10 [11] IO/3S READ indicates the type of operation that the bus controller is performing during a bus transaction. READ is driven by the MK50H28 only while it is the BUS MASTER. READ is valid during the entire bus transaction and is tristated at all other times. MK50H28 as a Bus Slave : READ = HIGH - Data is placed on the DAL lines by the chip. READ = LOW - Data is taken off the DAL lines by the chip. MK50H28 as a Bus Master : READ = HIGH - Data is taken off the DAL lines by the chip. READ = LOW - Data is placed on the DAL lines by the chip. INTR 11 [12] O/OD INTERRUPT is an attention interrupt line that indicates that one or more of the following CSR0 status flags is set: MISS, MERR, RINT, TINT or PINT. INTERRUPT is enabled by CSR0<09>, INEA=1. DALI 12 [13] O/3S DAL IN is an external bus transceiver control line. DALI is driven by the MK50H28 only while it is the BUS MASTER. DALI is asserted by the MK50H28 when it reads from the DAL lines during the data portion of a READ transfer. DALI is not asserted during a WRITE transfer. DALO 13 [14] O/3S DAL OUT is an external bus transceiver control line. DALO is driven by the MK50H28 only while it is the BUS MASTER. DALO is asserted by the MK50H28 when it drives the DAL lines during the address portion of a READ transfer or for the duration of a WRITE transfer. DAS 14 [15] IO/3S DATA STROBE defines the data portion of a bus transaction. By definition, data is stable and valid at the low to high transition of DAS. This signal is driven by the MK50H28 while it is the BUS MASTER. During the BUS SLAVE operation, this pin is used as an input. At all other times the signal is tristated. BMO BYTE BUSREL 15 [16] IO/3S I/O pins 15 and 16 are programmable through CSR4. If bit 06 of CSR4 is set to a one, pin 15 becomes input BUSREL and is used by the host to signal the MK50H28 to terminate a DMA burst after the current bus transfer has completed. If bit 06 is clear then pin 15 is an output and behaves as described below for pin 16. BM1 BUSAKO 16 [18] O/3S Pins 15 and 16 are programmable through bit 00 of CSR4 (BCON). If CSR4<00> BCON = 0, I/O PIN 15 = BMO (O/3S) I/O PIN 16 = BM1 (O/3S) BYTE MASK<1:0> Indicates the byte(s) on the DAL to be read or written during this bus transaction. MK50H28 drives these lines only as a Bus Master. MK50H28 ignores the BM lines when it is a Bus Slave. Byte selection is done as outlined in the following table. BM1 BM0 TYPE OF TRANSFER LOW LOW ENTIRE WORD LOW HIGH UPPER BYTE (DAL<15:08>) HIGH LOW LOWER BYTE (DAL<07:00>) HIGH HIGH NONE TAble 1 - PIN DESCRIPTION LEGEND: I Input only O Output only IO Input / Output 3S 3-State OD Open Drain (no internal pull-up) Note: Pin out for 52 pin PLCC is shown in brackets. MK50H28 4/64 |
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Similar Description - MK50H28 |
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