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TDA7479 Datasheet(PDF) 4 Page - STMicroelectronics |
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TDA7479 Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 8 page TDA7479 4/8 Figure 4. RDS timing diagram 3 OUTPUT TIMING The RDS (1187.5Hz) output clock on RDCL line is synchronized to the incoming data. According to the internal PLL lock condition data change can result on the falling or on the rising clock edge. (see Fig. 4)Whichever clock edge is used by the decoder (rising or falling edge) the data will remain valid for 416.7 µs after the clock transi- tion. 4 OSCILLATOR CONTROLS (FSEL, OSEL) Three different crystal frequencies can be used. The adaption of the internal clock divider to the external crystal is achieved via the input pin FSEL. See the following table for reference: Table 6. A special mode is introduced to reduce EMI. With pin OSEL connected to GND the internal oscillator is switched off and an external sinusoidal frequency could be applied on OSCIN. The peak to peak voltage of this signal can be reduced down to 60mV. In this mode the frequency selection via FSEL is still active. Suggested values of C1 and C2 are shown in the following table: Table 7. Crystal FSEL (pin configuration) 4.332MHz 8.664MHz 17.328MHz connected to GND or openconnected to Vs external resistor of 100K to Vs Crystal C1 C2 4.332MHz 8.664MHz 17.328MHz 27pF 27pF 27pF 47pF - - CLOCK LINE DATA LINE |
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