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M74HCT75RM13TR Datasheet(PDF) 1 Page - STMicroelectronics

Part # M74HCT75RM13TR
Description  4 BIT D TYPE LATCH
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M74HCT75RM13TR Datasheet(HTML) 1 Page - STMicroelectronics

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September 2001
s
HIGH SPEED :
tPD = 21ns (TYP.) at VCC = 4.5V
s
LOW POWER DISSIPATION:
ICC =2µA(MAX.) at TA=25°C
s
COMPATIBLE WITH TTL OUTPUTS :
VIH = 2V (MIN.) VIL = 0.8V (MAX)
s
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 75
DESCRIPTION
The M74HCT75 is an high speed CMOS 4 BIT D
TYPE LATCH fabricated with silicon gate C2MOS
technology.
It contains two groups of 2 bit latches controlled by
an enable input (G1
•2 or G3•4). These two latch
groups can be used in different circuits. Each latch
has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The
data applied to the data input is transferred to the
Q and Q outputs when the enable input is taken
high and the outputs will follow the data input as
long as the enable input is kept high. When the
enable input is taken low, the information data
applied to the data input is retained at the outputs.
The M74HCT75 is designed to directly interface
HSC2MOS
systems
with
TTL
and
NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT75
4 BIT D TYPE LATCH
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
M74HCT75B1R
SOP
M74HCT75M1R
M74HCT75RM13TR
TSSOP
M74HCT75TTR
TSSOP
DIP
SOP


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