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M74HC651 Datasheet(PDF) 1 Page - STMicroelectronics

Part No. M74HC651
Description  HC652 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE HC651 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE, INV.
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M74HC651 Datasheet(HTML) 1 Page - STMicroelectronics

 
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M74HC651
M74HC652
October 1993
HC652 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)
HC651 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)
B1R
(Plastic Package)
ORDER CODES :
M74HCXXXM1R
M74HCXXXB1R
M1R
(Micro Package)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN CONNECTIONS (top view)
.
HIGH SPEED
fMAX = 73 MHz (TYP.) AT VCC =5V
.
LOW POWER DISSIPATION
ICC =4
µA (MAX.) AT TA =25 °C
.
HIGH NOISE IMMUNITY
VNIH =VNIL =28 % VCC (MIN.)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
IOH =IOL = 6 mA (mIN.)
.
BALANCED PROPAGATION DELAYS
tPLH =tPHL
.
WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
.
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS651/652
DESCRIPTION
M74HC651/652 are high speed CMOS OCTAL
BUS TRANSCEIVERS AND REGISTERS (3-
STATE), fabricated in silicon gate C
2MOS technol-
ogy. They have the same high speed performance
of LSTTL combined with true CMOS low power con-
sumption. These devices consist of bus transceiver
circuits, D-type flip-flops, and control circuitry ar-
ranged for multiplexed transmission of data directly
from the input bus or from the internal storage reg-
isters. Enable GAB and GBA are provided to control
the transceiver functions.
Select AB and Select BA control pins are provided
to select whether real-time or stored data is trans-
fered. A low input level selects real-time data, and
a high selects stored data.
Data on the A or B bus, or both, can be stored in the
internal D flip-flops by low-to-high transitions at the
appropriate clock pins (CLOCK AB or CLOCK BA)
regardless of the select or enable control pins. When
select AB and select BA are in the real-time transfer
mode, it is also possible to store data without using
the internal D-type flip-flops by simultaneously en-
abling GAB and GBA. In this configuration each out-
put reinforces its input. Thus, when all other data
sources to the two sets of bus lines are at high im-
pedance, each set of bus lines will remain at its last
state. All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
GAB, GAB, CAB,
A, B
SAB, SBA, CBA
1/12


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