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ADS7867 Datasheet(PDF) 3 Page - Burr-Brown (TI) |
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ADS7867 Datasheet(HTML) 3 Page - Burr-Brown (TI) |
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3 / 22 page  www.ti.com ADS7884 SPECIFICATIONS ADS7884 ADS7885 SLAS567 – MARCH 2008 +VDD = 2.7 V to 5.5 V, TA = –40°C to 125°C, fsample = 2.5 MSPS for VDD = 2.7 V to 3.6 V, fsample = 3 MSPS for VDD = 3.6 V to 5.5 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input voltage span(1) 0 VDD V Absolute input voltage range +IN –0.20 VDD+0.20 V Ci Input capacitance(2) 27 pF IIlkg Input leakage current TA = 125°C 40 nA SYSTEM PERFORMANCE Resolution 10 Bits No missing codes 10 Bits INL Integral nonlinearity –0.8 ±0.3 0.8 LSB(3) DNL Differential nonlinearity –0.8 ±0.3 0.8 LSB EO Offset error(4)(5)(6) –1 ±0.2 1 LSB EG Gain error(5) –1 ±0.2 1 LSB SAMPLING DYNAMICS Conversion time 48-MHz SCLK, VDD = 5 V 224 240 ns Acquisition time 93.3 ns Maximum throughput rate 48-MHz SCLK, VDD = 5 V 3 MHz Aperture delay 10 ns DYNAMIC CHARACTERISTICS THD Total harmonic distortion(7) 100 kHz –81 dB SINAD Signal-to-noise and distortion 100 kHz 60 61.7 dB SFDR Spurious free dynamic range 100 kHz 81 dB Full power bandwidth At –3 dB 30 MHz DIGITAL INPUT/OUTPUT Logic family — CMOS VDD = 2.7 V to 3.6 V 1.5 5.5 VIH High-level input voltage V VDD = 3.6 V to 5.5 V 2.2 5.5 VDD = 5 V 0.8 VIL Low-level input voltage V VDD = 3 V 0.4 VOH High-level output voltage At Isource = 200 µA VDD–0.2 V VOL Low-level output voltage At Isink = 200 µA 0.4 POWER SUPPLY REQUIREMENTS +VDD Supply voltage 2.7 3.3 5.5 V At VDD = 3.0 V, 2.5-MSPS throughput 2.25 3 At VDD = 3.0 V, static state 1.8 Supply current (normal mode) mA At VDD = 5.0 V, 3-MSPS throughput 3 4 At VDD = 5.0 V, static state 2 SCLK off 1 Power down state supply current µA SCLK on (48 MHz) 90 200 VDD = 5 V, 3 MSPS 15 20 Power dissipation mW VDD = 3 V, 2.5 MSPS 6.8 (1) Ideal input span; does not include gain or offset error. (2) Refer to Figure 43 for details on sampling circuit (3) LSB means least significant bit (4) Measured relative to an ideal full-scale input (5) Offset error and gain error ensured by characterization. (6) First transition of 000H to 001H at (Vref/2 10) (7) Calculated on the first nine harmonics of the input frequency Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): ADS7884 ADS7885 |
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