V43648S04VCTG-10PC datasheet(4/12 Pages) MOSEL

Part #	V43648S04VCTG-10PC

Description	3.3 VOLT 8M x 64 HIGH PERFORMANCE PC100 UNBUFFERED SDRAM MODULE

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Manufacturer	MOSEL [Mosel Vitelic, Corp]

Direct Link	http://www.moselvitelic.com

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V43648S04V(C)TG-10PC Rev. 1.1 June 2000

MOSEL VITELIC

V43648S04V(C)TG-10PC

Serial Presence Detect Information

A serial presence detect storage device -

E2PROM - is assembled onto the module. Informa-

tion about the module configuration, speed, etc. is

written into the E2PROM device during module pro-

duction using a serial presence detect protocol (I2C

synchronous 2-wire bus)

SPD-Table:

Byte

Number

Function Described

SPD Entry Value

Hex Value

100 MHz

-10PC

0

Number of SPD bytes

128

80

1

Total bytes in Serial PD

256

08

2

Memory Type

SDRAM

04

3

Number of Row Addresses (without BS bits)

12

0C

4

Number of Column Addresses (for x8 SDRAM)

9

09

5

Number of DIMM Banks

1

01

6

Module Data Width

64

40

7

Module Data Width (continued)

0

00

8

Module Interface Levels

LVTTL

01

9

SDRAM Cycle Time at CL=3

10.0 ns

A0

10

SDRAM Access Time from Clock at CL=3

6.0 ns

60

11

Dimm Config (Error Det/Corr.)

none

00

12

Refresh Rate/Type

Self-Refresh, 15.6

µs

80

13

SDRAM width, Primary

x8

08

14

Error Checking SDRAM Data Width

n/a / x8

00

15

Minimum Clock Delay from Back to Back

Random Column Address

tccd = 1 CLK

01

16

Burst Length Supported

1, 2, 4, 8 & full Page

8F

17

Number of SDRAM Banks

4

04

18

Supported CAS Latencies

CL = 2 & 3

06

19

CS Latencies

CS Latency = 0

01

20

WE Latencies

WL = 0

01

21

SDRAM DIMM Module Attributes

Non Buffered/Non Reg.

00

22

SDRAM Device Attributes: General

Vcc tol

± 10%

0E

23

Minimum Clock Cycle Time at CAS Latency = 2

15.0 ns

F0

24

Maximum Data Access Time from Clock for CL = 2

9.0 ns

90

25

Minimum Clock Cycle Time at CL = 1

Not Supported

00

26

Maximum Data Access Time from Clock at CL = 1

Not Supported

00

27

Minimum Row Precharge Time tRP

20 ns

14

28

Minimum Row Active to Row Active Delay tRRD

20 ns

14

29

Minimum RAS to CAS Delay tRCD

20 ns

14

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