Electronic Components Datasheet Search |
|
GS1560ACF Datasheet(PDF) 8 Page - Gennum Corporation |
|
GS1560ACF Datasheet(HTML) 8 Page - Gennum Corporation |
8 / 80 page GS1560A/GS1561 Data Sheet 27360 - 10 January 2007 8 of 80 1.3 Pin Descriptions Table 1-1: Pin Descriptions Pin Number Name Timing Type Description 1 CP_VDD – Power Power supply connection for the charge pump. Connect to +3.3V DC analog. 2 PDBUFF_GND – Power Ground connection for the phase detector and serial digital input buffers. Connect to analog GND. 3 PD_VDD – Power Power supply connection for the phase detector. Connect to +1.8V DC analog. 4 BUFF_VDD – Power Power supply connection for the serial digital input buffers. Connect to +1.8V DC analog. 5 CD1 Non Synchronous Input STATUS SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the presence of a serial digital input signal. Normally generated by a Gennum automatic cable equalizer. When LOW, the serial digital input signal received at the DDI1 and DDI1 pins is considered valid. When HIGH, the associated serial digital input signal is considered to be invalid. In this case, the LOCKED signal is set LOW and all parallel outputs are muted. 6, 8 DDI1, DDI1 Analog Input Differential input pair for serial digital input 1. 7 TERM1 Analog Input Termination for serial digital input 1. AC couple to EQ_GND. 9 DVB_ASI Non Synchronous Input / Output CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. This pin will be an input set by the application layer in slave mode, and will be an output set by the device in master mode. Master Mode (MASTER/SLAVE = HIGH) The DVB_ASI signal will be HIGH only when the device has locked to a DVB-ASI compliant data stream. It will be LOW otherwise. Slave Mode (MASTER/SLAVE = LOW) When set HIGH in conjunction with SD/HD = HIGH and SMPTE_BYPASS = LOW, the device will be configured to operate in DVB-ASI mode. When set LOW, the device will not support the decoding or word alignment of received DVB-ASI data. 10 IP_SEL Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select DDI1 / DDI1 or DDI2 / DDI2 as the serial digital input signal, and CD1 or CD2 as the carrier detect input signal. When set HIGH, DDI1 / DDI1 is selected as the serial digital input and CD1 is selected as the carrier detect input signal. When set LOW, DDI2 / DDI2 serial digital input and CD2 carrier detect input signal is selected. |
Similar Part No. - GS1560ACF |
|
Similar Description - GS1560ACF |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |