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M58WR128ET Datasheet(PDF) 69 Page - STMicroelectronics |
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M58WR128ET Datasheet(HTML) 69 Page - STMicroelectronics |
69 / 87 page 69/87 M58WR128ET, M58WR128EB Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 con- tains the banks that are made up of the parameter and main blocks. (P+35)h =6Eh 03h (P+3D)h =76h 03h Bank Region 2 (Erase Block Type 1): Page mode and synchronous mode capabilities (defined in table 10) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+36)h =6Fh 07h Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+37)h =70h 00h (P+38)h =71h 20h (P+39)h =72h 00h (P+3A)h =73h 64h Bank Region 2 (Erase Block Type 2) Minimum block erase cycles × 1000 (P+3B)h =74h 00h (P+3C)h =75h 01h Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved (P+3D)h =76h 03h Bank Region 2 (Erase Block Type 2): Page mode and synchronous mode capabilities (defined in table 10) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+3E)h =77h (P+3E)h =77h Feature Space definitions (P+3F)h =78h (P+3F)h =78h Reserved M58WR128ET (top) M58WR128EB (bottom) Description Offset Data Offset Data |
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