Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

V436416S04VCTG-75 Datasheet(PDF) 4 Page - Mosel Vitelic, Corp

Part No. V436416S04VCTG-75
Description  3.3 VOLT 16M x 64 HIGH PERFORMANCE PC133 UNBUFFERED SDRAM MODULE
Download  12 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  MOSEL [Mosel Vitelic, Corp]
Homepage  http://www.moselvitelic.com
Logo 

V436416S04VCTG-75 Datasheet(HTML) 4 Page - Mosel Vitelic, Corp

 
Zoom Inzoom in Zoom Outzoom out
 4 / 12 page
background image
4
V436416S04V(C)TG-75 Rev. 1.7 September 2001
MOSEL VITELIC
V436416S04V(C)TG-75
Serial Presence Detect Information
A serial presence detect storage device -
E2PROM - is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
writtenintothe E2PROM device during module pro-
duction using a serial presence detect protocol (I2C
synchronous 2-wire bus)
SPD-Table for PC133 modules:
Byte Number
Function Described
SPD Entry Value
Hex Value
16Mx64
0
Number of SPD bytes
128
80
1
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses (without BS bits)
12
0C
4
Number of Column Addresses (for x8 SDRAM)
9
09
5
Number of DIMM Banks
2
02
6
Module Data Width
64
40
7
Module Data Width (continued)
0
00
8
Module Interface Levels
LVTTL
01
9
SDRAM Cycle Time at CL=3
7.5 ns
75
10
SDRAM Access Time from Clock at CL=3
5.4 ns
54
11
Dimm Config (Error Det/Corr.)
none
00
12
Refresh Rate/Type
Self-Refresh, 15.6
µs80
13
SDRAM width, Primary
x8
08
14
Error CheckingSDRAMDataWidth
n/a/ x8
00
15
Minimum Clock Delay from Back to Back Random
Column Address
tccd =1CLK
01
16
Burst Length Supported
1, 2, 4, 8 & full Page
8F
17
Number of SDRAM Banks
4
04
18
Supported CAS Latencies
CL = 2, 3
06
19
CS Latencies
CS Latency = 0
01
20
WE Latencies
WL = 0
01
21
SDRAM DIMM Module Attributes
Non Buffered/Non Reg.
00
22
SDRAM Device Attributes: General
Vcc tol ± 10%
0E
23
MinimumClock CycleTimeat CAS Latency = 2
10.0 ns
A0
24
Maximum Data Access Time from Clock for CL = 2
6.0 ns
60
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
26
Maximum Data Access Time from Clock at CL = 1
Not Supported
00
27
Minimum Row Precharge Time
20 ns
14
28
Minimum Row Active to Row Active Delay tRRD
15 ns
0F
29
Minimum RAS to CAS Delay tRCD
20 ns
14
30
Minimum RAS Pulse Width tRAS
45 ns
2D


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn