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AAT2782 Datasheet(PDF) 18 Page - Advanced Analogic Technologies

Part No. AAT2782
Description  Triple Output PMIC: Dual Buck with Low-VIN LDO
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Maker  ANALOGICTECH [Advanced Analogic Technologies]
Homepage  http://www.analogictech.com

AAT2782 Datasheet(HTML) 18 Page - Advanced Analogic Technologies

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Triple Output PMIC: Dual Buck with Low-VIN LDO
www .analogictech.com
IQ is the step-down converter quiescent current. The
term tsw is used to estimate the full load step-down con-
verter switching losses. For the condition where the
step-down converter is in dropout at 100% duty cycle,
the total device dissipation reduces to:
PTOTAL(Step-down) = IO2 · RDSON(H) + IQ · VIN
Since RDS(ON), quiescent current, and switching losses all
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range.
The AAT2782 LDO is designed to deliver a continuous
output load current up to 400mA under normal operating
conditions. The limiting characteristic for the maximum
output load safe operating area is essentially package
power dissipation and the internal preset thermal limit of
the device. In order to obtain high operating currents,
careful device layout and circuit operating conditions
must be taken into account.
This calculation accounts for the total power dissipation
of the LDO regulator, including that caused by ground
Add the total losses of the two step-down converters and
the LDO to determine the max junctions temperature.
The maximum junction temperature can be derived from
the ΘJA for the TDFN34-16 which is 50°C/W.
The suggested PCB layout for the AAT2782 is shown in
Figures 2 and 3. The following guidelines should be used
to help ensure a proper layout.
1. The power input capacitors (C6) should be connected
as closely as possible to VP1 and VP2, The LDO input
capacitor (C3) should be close to VIN3 as shown in
Figure 2. Due to the pin placement of VP1, VP2 and
VIN3 for all converters, proper decoupling is not pos-
sible with just one input capacitor.
2. C4 is a bypass capacitor for the VIN supply pin for
the device.
3. C8 and L1, C5 and L2 should be connected as close-
ly as possible. The connection of L1 and L2 to the
LX1 and LX2 pins should be as short as possible.
4. The feedback trace or FB pin should be separate
from any power trace and connect as closely as pos-
sible to the load point. Sensing along a high-current
load trace will degrade DC load regulation.
5. The resistance of the trace from the load returns to
GND1, GND2, and AGND should be kept to a mini-
mum. This will help to minimize any error in DC
regulation due to differences in the potential of the
internal signal ground and the power ground.
6. Connect unused signal pins to ground to avoid
unwanted noise coupling.
7. For good thermal coupling, PCB vias are required
from the pad for the TDFN paddle to the ground
plane. The via diameter should be 0.3mm to 0.33mm
and positioned on a 1.2mm grid.

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