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BAND-GAP VOLTAGE AND BIAS GENERATION

TERMINAL ASSIGNMENTS

1

2

3

4

LOS

SD

SCK

SDA

RGV PACKAGE

(TOP VIEW)

12

11

10

9

16

TH

RTHI

15

14

13

5

6

7

8

P0030-01

ONET4291PA

SLLS671 – SEPTEMBER 2005

This voltage is referred to GND.

On-chip band-gap voltage circuitry generates a reference voltage, independent of supply voltage, from which all

other internally required voltages and bias currents are derived.

For the ONET4291PA, a small-footprint 4-mm

× 4-mm, 16-terminal QFN package is used, with a terminal pitch of

0,65 mm.

TERMINAL DESCRIPTION

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

Offset cancellation filter capacitor plus terminal. An external 0.1-

µF filter capacitor must be

COC+

6

Analog

connected between this terminal and COC– (terminal 5).

Offset cancellation filter capacitor minus terminal. An external 0.1-

µF filter capacitor must be

COC–

5

Analog

connected between this terminal and COC+ (terminal 6).

Non-inverted data input. On-chip 50-

Ω terminated to COC+. Differentially 100-Ω terminated

DIN+

7

Analog input

to DIN–.

Inverted data input. On-chip 50-

Ω terminated to COC–. Differentially 100-Ω terminated to

DIN–

8

Analog input

DIN+.

DOUT+

15

CML output

Non-inverted data output. On-chip 50-

Ω back-terminated to V

DOUT–

14

CML output

Inverted data output. On-chip 50-

Ω back-terminated to V

GND

13, 16, EP

Supply

Circuit ground. Exposed die pad (EP) must be grounded.

Open-drain

High level indicates that the input signal amplitude is below the programmed threshold level.

LOS

1

MOS

Open-drain output. Requires an external 10-k

Ω pullup resistor to V

Digitally controlled internal resistor to ground, which can be used for LOS threshold

RTHI

9

Analog

adjustment. A 6-bit-wide control register can be set via the two-wire interface.

SCK

3

CMOS input

Two-wire interface serial clock. Includes a 100-k

Ω pullup resistor to V

High level indicates that sufficient input signal amplitude is applied to the device. Low level

SD

2

CMOS output

indicates that the input signal amplitude is below the programmed threshold level.

SDA

4

CMOS input

Two-wire interface serial data input. Includes a 100-k

Ω pullup resistor to V

LOS threshold adjustment with resistor to GND. For use of the internal digitally controlled

TH

10

Analog input

resistor, connect TH with RTHI (terminal 9).

11, 12

Supply

3.3-V, +10%/–12% supply voltage

8