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SN74LV4046A Datasheet(PDF) 6 Page - Texas Instruments |
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SN74LV4046A Datasheet(HTML) 6 Page - Texas Instruments |
6 / 15 page www.ti.com SIGIN, COMPIN PCPOUT, PC1OUT, VS tPHL tPLH tTHL tTLH VS PC3OUT Inputs Outputs SIGIN Inputs COMPIN Inputs PC2OUT Output VS tPZH VS tPHZ tPZL tPLZ VS 90% 10% SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 APPLICATION INFORMATION (continued) Figure 7. Input-to-Output Propagation Delays and Figure 8. 3-State Enable and Disable Times for PC2OUT Output Transition Times CPD (1) CHIP SECTION CPD UNIT Comparator 1 120 pF VCO 120 (1) R1 between 3 k Ω and 50 kΩ R2 between 3 k Ω and 50 kΩ R1 + R2 parallel value > 2.7 k Ω C1 > 40 pF 6 Submit Documentation Feedback |
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