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S70GL01GN00 Datasheet(PDF) 4 Page - SPANSION |
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S70GL01GN00 Datasheet(HTML) 4 Page - SPANSION |
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4 / 83 page  2 S70GL01GN00 MirrorBitTM Flash S70GL01GN00_00_A2 May 21, 2007 Da ta S h e e t General Description The S70GL01GN00 is a 1024 Mbit, single power supply flash memory device or- ganized as two S29GL512N dies in a single 64-ball Fortified-BGA package. Each S29GL512N die is 512 Mbit, organized as 33,554,432 words or 67,108,864 bytes. The devices have a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system or in standard EPROM programmers. Access times as fast as 110 ns is available. Note that each access time has a spe- cific operating voltage range (VCC) and an I/O voltage range (VIO), as specified in the Product Selector Guide‚ on page 5 and the Ordering Information‚ on page 9. The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA pack- age. Each device has separate chip enable (CE# or CE2#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a VCC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased cur- rent. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The devices are entirely command set compatible with the JEDEC single- power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and repro- grammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation starts, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/ BY#) output to determine whether the operation is complete. To facilitate pro- gramming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. Hardware data protection measures include a low VCC detector that automat- ically inhibits write operations during power transitions. Persistent Sector Protection provides in-system, command-enabled protection of any combina- tion of sectors using a single power supply at VCC. Password Sector Protection prevents unauthorized write and erase operations in any combination of sectors through a user-defined 64-bit password. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume fea- ture enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. |
Similar Part No. - S70GL01GN00_07 |
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Similar Description - S70GL01GN00_07 |
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