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ICS9LPR426A Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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ICS9LPR426A Datasheet(HTML) 3 Page - Integrated Circuit Systems |
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3 Integrated Circuit Systems, Inc. ICS9LPR426A Advance Information 1346—10/23/07 Pin Description (Continued) PIN # PIN NAME TYPE DESCRIPTION 29 GND PWR Ground pin. 30 PCIeC_L4 OUT Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND needed) 31 PCIeT_L4 OUT True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed) 32 PEREQ2#/PCIeC_L5 I/O Real-time input pin that controls PCIEXCLK outputs that are selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of differential low power PCI Express output. No 50ohm resistor to GND needed. 33 PEREQ1#/PCIeT_L5 I/O Real-time input pin that controls PCIEXCLK outputs that are selected through the I2c. 1 = disabled, 0 = enabled. / True clock of differential low power PCI Express output. No 50ohm resistor to GND needed. 34 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V 35 CPUITPC_L2/PCIeC_L6 OUT Complement clock of differential pair CPU output. / Complement clock of differential PCIEX pair. These are 0.8V push pull outputs. No 50ohm resistor to GND needed. 36 CPUITPT_L2/PCIeT_L6 OUT True clock of differential pair CPU output. / True clock of differential PCIEX pair. These are 0.8V push pull outputs. No 50ohm resistor to GND needed. 37 VDDA PWR 3.3V power for the PLL core. 38 GNDA PWR Ground pin for the PLL core. 39 VDD PWR Power supply, nominal 3.3V 40 CPUC_L1 OUT Complementary clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor to GND needed. 41 CPUT_L1 OUT True clock of differential pair 0.8V push-pull CPU outputs. No 50 ohm resistor to GND needed. 42 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 43 CPUC_L0 OUT Complementary clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor to GND needed. 44 CPUT_L0 OUT True clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor to GND needed. 45 GND PWR Ground pin. 46 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 47 SDATA I/O Data pin for SMBus circuitry, 3.3V tolerant. 48 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 49 X2 OUT Crystal output, Nominally 14.318MHz 50 X1 IN Crystal input, Nominally 14.318MHz. 51 GND PWR Ground pin. 52 REF0 OUT 14.318 MHz reference clock. 53 REF1/FSLC/TEST_SEL I/O 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table 54 CPU_STOP# IN Stops all CPU clocks, except those set to be free running clocks 55 PCI&PCIEX_STOP# IN Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input. 56 PCICLK2/REQ_SEL** I/O 3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ# |
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