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ICS9LPR426A Datasheet(PDF) 2 Page - Integrated Circuit Systems

Part No. ICS9LPR426A
Description  Low Power Programmable Timing Control Hub™ for P4™ processor
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Maker  ICST [Integrated Circuit Systems]
Homepage  http://www.icst.com
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ICS9LPR426A Datasheet(HTML) 2 Page - Integrated Circuit Systems

 
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2
Integrated
Circuit
Systems, Inc.
ICS9LPR426A
Advance Information
1346—10/23/07
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
2
GND
PWR
Ground pin.
3
PCICLK3
OUT
PCI clock output.
4
PCICLK4
OUT
PCI clock output.
5
*SELPCIEX0_LCD#PCICLK5
I/O
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX / 3.3V PCI clock
output.
6
GND
PWR
Ground pin.
7
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
8
ITP_EN/PCICLK_F0
I/O
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
9
*SELLCD_27#/PCICLK_F1
I/O
Free running PCI clock not affected by PCI_STOP#.
SELLCD_27#: latched input to select pin functionality
1 = LCDCLK pair
0 = 27MHzSS/27MHzSS# pair
10
Vtt_PwrGd#/PD
IN
Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be
sampled. PD is an asynchronous active high input pin used to put the device into a low
power state. The internal clocks, PLLs and the crystal oscillator are stopped.
11
VDD48
PWR
Power pin for the 48MHz output.3.3V
12
FSLA/USB_48MHz
I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics
for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V.
13
GND
PWR
Ground pin.
14
DOTT_96MHzL
OUT
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm to GND
needed.
15
DOTC_96MHzL
OUT
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed.
16
FSLB/TEST_MODE
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics
for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z
and REF/N divider mode while in test mode. Refer to Test Clarification Table.
17
27FIX/LCD_SSCGT/PCIeT_L0
OUT
27MHz Non-Spread Push-Pull output / True clock of low power LCDCLK output / True
clock of low power PCIEXCLK differential pair/ selected by SELPCIEX0_LCD# and
SELLCD_27#. No 50ohm resistor to GND needed for differential outputs.
18
27SS/LCD_SSCGC/PCIeC_L0
OUT
27MHz Spreading Push-Pull output / Complementary clock of LCDCLK_SS output /
Complementary clock of PCIEXCLK differential pair/ selected by SELPCIEX0_LCD# and
SELLCD_27#. No 50ohm resistor to GND needed for differential outputs.
19
PCIeT_L1
OUT
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
20
PCIeC_L1
OUT
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
21
VDDPCIEX
PWR
Power supply for PCI Express clocks, nominal 3.3V
22
PCIeT_L2
OUT
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
23
PCIeC_L2
OUT
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
24
PCIeT_L3
OUT
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
25
PCIeC_L3
OUT
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
26
SATACLKT_L
OUT
True clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND needed)
27
SATACLKC_L
OUT
Complement clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND
needed)
28
VDDPCIEX
PWR
Power supply for PCI Express clocks, nominal 3.3V


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