Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6279

9

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Undervoltage Lockout

The A6278 and A6279 include an internal under-voltage lockout

(UVLO) circuit that disables the outputs in the event that the

logic supply voltage drops below a minimum acceptable level.

This feature prevents the display of erroneous information, a

necessary function for some critical applications.

Upon recovery of the logic supply voltage after a UVLO event,

and on power-up, all internal shift registers and latches are set

to 0. The A6278/A6279 is then in Normal mode.

Output Staggering Delay

The A6278/A6279 has a 20 ns delay between each output. The

staggering of the outputs reduces the in-rush of currents onto the

power and ground planes. This aids in power supply decoupling

and EMI/EMC reduction.

The output staggering delay occurs under the following condi-

tions:

• OUTPUT ENABLE is pulled low

• OUTPUT ENABLE is held low and LATCH ENABLE is

pulled high

• OUTPUT ENABLE is held low, LATCH ENABLE is held high,

and CLOCK is pulled high

The 20 ns delays are cumulative across all the outputs. Under any

of the above conditions, the state of OUT0 gets set after a typical

and so forth. In the A6279, OUT15 will get set after 300 ns (15 ×

Note: The maximum CLOCK frequency is reduced in applica-

tions where both the OUTPUT ENABLE pin is held low and the

LATCH ENABLE pin is held high continuously, and the outputs

change state on the CLOCK edges. The staggering delay could

cause spurious output responses at CLOCK speeds greater than

1 MHz.

Thermal Shutdown

When the junction temperature of the A6278/A6279 reaches the

the outputs are shut off until the junction temperature cools down

The shift register and output latches will remain active during

a TSD event. Therefore, there is no need to reset the data in the

output latches.

In LED OCD mode, if the junction temperature reaches the Ther-

mal Shut Down threshold, the outputs will turn off, as in Normal

mode operation. However, all of the shift registers will be set

with 0, the error bit value.