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M93C86 Datasheet(PDF) 19 Page - STMicroelectronics |
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M93C86 Datasheet(HTML) 19 Page - STMicroelectronics |
19 / 37 page M93C86, M93C76, M93C66, M93C56, M93C46 Clock pulse counter 19/37 9 Clock pulse counter In a noisy environment, the number of pulses received on Serial Clock (C) may be greater than the number delivered by the master (the microcontroller). This can lead to a misalignment of the instruction of one or more bits (as shown in Figure 7.) and may lead to the writing of erroneous data at an erroneous address. To combat this problem, the M93Cx6 has an on-chip counter that counts the clock pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL instruction is aborted, and the contents of the memory are not modified. The number of clock cycles expected for each instruction, and for each member of the M93Cx6 family, are summarized in Table 5. to Table 7.. For example, a Write Data to Memory (WRITE) instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization) from the start bit to the falling edge of Chip Select Input (S). That is: 1 Start bit + 2 Op-code bits + 9 Address bits + 8 Data bits Figure 7. Write sequence with one clock glitch AI01395 S An-1 C D WRITE START D0 "1" "0" An Glitch An-2 ADDRESS AND DATA ARE SHIFTED BY ONE BIT |
Similar Part No. - M93C86_08 |
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Similar Description - M93C86_08 |
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