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74HC164 Datasheet(PDF) 1 Page - STMicroelectronics |
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74HC164 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 12 page  M54HC164 M74HC164 October 1992 8 BIT SIPO SHIFT REGISTER B1R (Plastic Package) ORDER CODES : M54HC164F1R M74HC164M1R M74HC164B1R M74HC164C1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No Internal Connection . HIGH SPEED tPD = 15 ns (TYP.) AT VCC =5 V . LOW POWER DISSIPATION ICC =4 µA (MAX.) AT TA =25 °C . OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS . BALANCED PROPAGATION DELAYS tPLH =tPHL . SYMMETRICAL OUTPUT IMPEDANCE IOL = IOH = 4 mA (MIN.) . HIGH NOISE IMMUNITY VNIH =VNIL =28 % VCC (MIN.) . WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V . PIN AND FUNCTION COMPATIBLE WITH 54/74LS164 DESCRIPTION The M54/74HC164 is a high speed CMOS 8 BIT SIPO SHIFT REGISTER fabricated in silicon gate C 2MOS technology. It has the same high speed per- formance of LSTTL combined with true CMOS low power consumption. The HC164 is an 8 bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B), either of these inputs can be used as an active high enable for data entry through the other input. An unused input must be high, or both inputs con- nected together. Each low-to-high transition on the clock input shifts data one place to the right and enters into QA, the logic NAND of the two data inputs (A ⋅ B), the data that existed before the rising clock edge. A low level on the clear input overrides all other inputs and clears the register asynchronously, forcing all Q outputs low. All inputs are equipped with protection circuits against static discharge and transient excess volt- age. 1/12 |
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