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M50LPW116 Datasheet(PDF) 8 Page - STMicroelectronics |
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M50LPW116 Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 36 page M50LPW116 8/36 Table 6. LPC Bus Read Field Definitions Clock Cycle Number Clock Cycle Count Field LAD0- LAD3 Memory I/O Description 1 1 START 0000b I On the rising edge of CLK with LFRAME Low, the contents of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle. 21 CYCTYPE + DIR 0100b I Indicates the type of cycle and selects 1-byte reading. Bits 3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b for read. Bit 0 is reset to 0. 3-10 8 ADDR XXXX I A 32-bit address phase is transferred starting with the most significant nibble first. A26-A31 must be set to 1. A22 = 1 for Array, A22 = 0 for registers access. For A21, A23- A25 values, refers to Table 2. 11 1 TAR 1111b I The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. 12 1 TAR 1111b (float) O The LPC Flash Memory takes control of LAD0-LAD3 during this cycle. 13-14 2 WSYNC 0101b O The LPC Flash Memory drives LAD0-LAD3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included. 15 1 RSYNC 0000b O The LPC Flash Memory drives LAD0-LAD3 to 0000b, indicating that data will be available during the next clock cycle. 16-17 2 DATA XXXX O Data transfer is two CLK cycles, starting with the least significant nibble. 18 1 TAR 1111b O The LPC Flash Memory drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. 19 1 TAR 1111b (float) N/A The LPC Flash Memory floats its outputs, the host takes control of LAD0-LAD3. Figure 4. LPC Bus Read Waveforms AI04429 CLK LFRAME LAD0-LAD3 Number of clock cycles START CYCTYPE + DIR ADDR TAR SYNC DATA TAR 1182322 |
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