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M50LPW041 Datasheet(PDF) 4 Page - STMicroelectronics

Part No. M50LPW041
Description  4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory
Download  37 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M50LPW041 Datasheet(HTML) 4 Page - STMicroelectronics

 
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SIGNAL DESCRIPTIONS
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con-
figuration Pin, IC.
The signals for each interface are discussed in the
Low Pin Count (LPC) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply sig-
nals are discussed in the Supply Signal Descrip-
tions section below.
Low Pin Count (LPC) Signal Descriptions
For the Low Pin Count (LPC) Interface see Figure
1, Logic Diagram, and Table 1, Signal Names.
Input/Output Communications (LAD0-LAD3). All
Input and Output Communication with the memory
take place on these pins. Addresses and Data for
Bus Read and Bus Write operations are encoded
on these pins.
Input Communication Frame (LFRAME). The
Input Communication Frame (LFRAME) signals
the start of a bus operation. When Input Commu-
nication Frame is Low, VIL, on the rising edge of
the Clock a new bus operation is initiated. If Input
Communication Frame is Low, VIL, during a bus
operation then the operation is aborted. When In-
put Communication Frame is High, VIH, the cur-
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID3). The Identification
Inputs (ID0-ID3) allow to address up to 16
memories on a bus. The value on addresses A19-
A22 is compared to the hardware strapping on the
ID0-ID3 pins to select which memory is being
addressed, as shown in Table 2.
General Purpose Inputs (GPI0-GPI4). The Gener-
al Purpose Inputs can be used as digital inputs for
the CPU to read. The General Purpose Input Reg-
ister holds the values on these pins. The pins must
have stable data from before the start of the cycle
that reads the General Purpose Input Register un-
til after the cycle is complete. These pins must not
be left to float, they should be driven Low, VIL, or
High, VIH.
Interface Configuration (IC). The Interface Con-
figuration input selects whether the Low Pin Count
(LPC) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
Table 2. Memory Identification Input Configuration
Memory
Number
ID2
ID2
ID1
ID0
Top
Bottom
A
22
A
21
A
20
A
19
A
22
A
21
A
20
A
19
1 (Boot)
VIL or floating VIL or floating VIL or floating VIL or floating
11
11
000
1
2
VIL or floating VIL or floating VIL or floating
VIH
11
10
000
0
3
VIL or floating VIL or floating
VIH
VIL or floating
11
01
001
1
4
VIL or floating VIL or floating
VIH
VIH
11
00
001
0
5
VIL or floating
VIH
VIL or floating VIL or floating
10
11
010
1
6
VIL or floating
VIH
VIL or floating
VIH
10
10
010
0
7
VIL or floating
VIH
VIH
VIL or floating
10
01
011
1
8
VIL or floating
VIH
VIH
VIH
10
00
011
0
9
VIH
VIL or floating VIL or floating VIL or floating
01
11
100
1
10
VIH
VIL or floating VIL or floating
VIH
01
10
100
0
11
VIH
VIL or floating
VIH
VIL or floating
01
01
101
1
12
VIH
VIL or floating
VIH
VIH
01
00
101
0
13
VIH
VIH
VIL or floating VIL or floating
00
11
110
1
14
VIH
VIH
VIL or floating
VIH
00
10
110
0
15
VIH
VIH
VIH
VIL or floating
00
01
111
1
16
VIH
VIH
VIH
VIH
00
00
111
0


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