Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

M50LPW041 Datasheet(PDF) 3 Page - STMicroelectronics

Part No. M50LPW041
Description  4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory
Download  37 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo 

M50LPW041 Datasheet(HTML) 3 Page - STMicroelectronics

 
Zoom Inzoom in Zoom Outzoom out
 3 / 37 page
background image
3/37
M50LPW041
Figure 4. TSOP Connections
AI06872
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A9
A8
W
VSS
VCC
DQ7
G
RB
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
ID1
LAD1
LAD2
GPI3
TBL
ID2
GPI0
WP
NC
VCC
NC
IC (VIL)
RFU
GPI4
NC
VSS
LFRAME
RFU
LAD3
VSS
VCC
RFU
RFU
NC
CLK
RP
NC
VPP
VCC
NC
M50LPW041
10
1
11
20
21
30
31
40
ID3
NC
INIT
NC
RFU
GPI2
LAD0
GPI1
ID0
VSS
NC
NC
NC
IC (VIH)
NC
NC
NC
NC
RC
RP
VPP
VCC
NC
A10
VSS
VSS
VCC
Table 1. Signal Names (LPC Interface) Memory
LAD0-LAD3
Input/Output Communications
LFRAME
Input Communication Frame
ID0-ID3
Identification Inputs
GPI0-GPI4
General Purpose Inputs
IC
Interface Configuration
RP
Interface Reset
INIT
CPU Reset
CLK
Clock
TBL
Top Block Lock
WP
Write Protect
RFU
Reserved for Future Use. Leave
disconnected or set at VIL or VIH.
VCC
Supply Voltage
VPP
Optional Supply Voltage for Fast
Erase Operations
VSS
Ground
NC
Not Connected Internally
designed to remove the need for the ISA bus in
current PC Chipsets; the M50LPW041 acts as the
PC BIOS on the Low Pin Count bus for these PC
Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in a PLCC32 or TSOP40
(10mm x 20mm) package and is supplied with all
the bits erased (set to 1).
System Memory Mapping
The LPC address sequence is 32 bits long. The
M50LPW041 responds to addresses mapped to
the top of the 4 GByte memory space, from
FFFF FFFFh. Address bits A31-A24 must be set
to 1. A23 is set to 1 for array access, and to 0 for
register access.
The M50LPW041 also responds to addresses
mapped to the bottom of the 4 GByte memory
space, from 0000 0000h. Address bits A31-A24
must be set to 0. A23 is set to 0 for array access,
and to 1 for register access.
For A22-A19, see Table 2. A18-A0 are for array
addresses.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn