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M50LPW041 Datasheet(PDF) 10 Page - STMicroelectronics |
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M50LPW041 Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 37 page M50LPW041 10/37 Table 8. LPC Bus Write Field Definitions Clock Cycle Number Clock Cycle Count Field LAD0- LAD3 Memory I/O Description 1 1 START 0000b I On the rising edge of CLK with LFRAME Low, the contents of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle. 21 CYCTY PE + DIR 011Xb I Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1 indicates the direction of transfer: 1b for write. Bit 0 is don’t care (X). 3-10 8 ADDR XXXX I A 32-bit address phase is transferred starting with the most significant nibble first. See Tables 3, 2 and 6 for the field description. 11-12 2 DATA XXXX I Data transfer is two cycles, starting with the least significant nibble. 13 1 TAR 1111b I The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. 14 1 TAR 1111b (float) O The LPC Flash Memory takes control of LAD0-LAD3 during this cycle. 15 1 SYNC 0000b O The LPC Flash Memory drives LAD0-LAD3 to 0000b, indicating it has received data or a command. 16 1 TAR 1111b O The LPC Flash Memory drives LAD0-LAD3 to 1111b, indicating a turnaround cycle. 17 1 TAR 1111b (float) N/A The LPC Flash Memory floats its outputs and the host takes control of LAD0-LAD3. Figure 6. LPC Bus Write Waveforms AI04430 CLK LFRAME LAD0-LAD3 Number of clock cycles START CYCTYPE + DIR ADDR DATA TAR SYNC TAR 1182212 |
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