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M50LPW002 Datasheet(PDF) 4 Page - STMicroelectronics

Part No. M50LPW002
Description  2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M50LPW002 Datasheet(HTML) 4 Page - STMicroelectronics

 
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M50LPW002
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SUMMARY DESCRIPTION
The M50LPW002 is a 2 Mbit (256Kb x8) non-vola-
tile memory that can be read, erased and repro-
grammed. These operations can be performed
using a single low voltage (3.0 to 3.6V) supply. For
fast programming and fast erasing in production
lines an optional 12V power supply can be used to
reduce the programming and the erasing times.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental Pro-
gram or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
The device features an asymmetrical blocked ar-
chitecture. The device has an array of 7 blocks:
s
1 Boot Block of 16 KByte
s
2 Parameter Blocks of 8 KByte each
s
1 Main Block of 32 KByte
s
3 Main Blocks of 64 KByte each
Two different bus interfaces are supported by the
memory. The primary interface is the Low Pin
Count (or LPC) Standard Interface. This has been
designed to remove the need for the ISA bus in
current PC Chipsets; the M50LPW002 acts as the
PC BIOS on the Low Pin Count bus for these PC
Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is delivered with all the bits erased
(set to 1).
Figure 2. PLCC Connections
Note: Pins 27 and 28 are not internally connected.
AI05744
NC
LFRAME
17
ID1
ID0
LAD0
GPI1
TBL
ID3
ID2
GPI0
WP
9
VSS
1
VCC
NC
RFU
32
M50LPW002
IC (VIL)
INIT
RFU
25
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
NC
W
VSS
VCC
NC
DQ7
IC (VIH)
G
RB
A/A Mux
A/A Mux
A/A Mux
A/A Mux


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