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MAX5631 Datasheet(PDF) 13 Page - Maxim Integrated Products

Part No. MAX5631
Description  16-Bit DACs with 32-Channel Sample-and-Hold Outputs
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5631 Datasheet(HTML) 13 Page - Maxim Integrated Products

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sequencer resumes normal operation at the interrupted
channel 7.
Burst Mode
Burst Mode allows multiple SRAM locations to be
loaded at high speed. During Burst Mode, the output
voltages are not updated until the data burst is com-
plete and control returns to the sequencer. Select Burst
Mode by driving both IMMED and C1 low.
The sequencer is interrupted when
CS is taken low. All
or part of the memory can be loaded while
CS is low.
Each data word is loaded into its specified SRAM
address. The DAC conversion and SHA sample in
progress are completely transparent to the serial bus
activity. When
CS is taken high, the sequencer resumes
scrolling at the interrupted SRAM address. New values
are updated when their turn comes up in the sequence.
After Burst Mode is used, it is recommended that at
least one full sequencer loop (320µs) is allowed to
occur before the serial port is accessed again. This
ensures that all outputs are updated before the
sequencer is interrupted.
Figure 6 shows an example of a burst mode operation.
As with the immediate update example,
CS falls while
channel 7 is being refreshed. Data for multiple chan-
nels is loaded, and no channels are refreshed as long
as
CS remains low. Once CS returns high, sequencing
resumes with channel 7 and continues normal refresh
operation. Thirty-three fSEQ cycles are required before
all channels have been updated.
External Sequencer Clock
An external clock may be used to control the
sequencer, altering the output update rate. The
sequencer runs at 1/4 the frequency of the supplied
clock (ECLK). The external clock option is selected by
driving either C0 or CLKSEL high.
When CLKSEL is asserted, the internal clock oscillator
is disabled. This feature allows synchronizing the
sequencer to other system operations, or shutting down
of the sequencer altogether during high-accuracy sys-
tem measurements. The low 1mV/s droop of these
devices ensures that no appreciable degradation of the
output voltages occurs, even during extended periods
of time when the sequencer is disabled.
Power-On Reset
A power-on reset (POR) circuit sets all channels to 0V
(code 4F2C hex) in sequence, requiring 320µs. This
prevents damage to downstream ICs due to arbitrary
reference levels being presented following system
power-up. This same function is available by driving
RST low. During the reset operation, the sequencer is
run by the internal clock, regardless of the state of
CLKSEL. The reset process cannot be interrupted, seri-
al inputs will be ignored until the entire reset process is
complete.
Applications Information
Power Supplies and Bypassing
Grounding and power-supply decoupling strongly influ-
ence device performance. Digital signals may couple
through the reference input, power supplies, and
ground connection. Proper grounding and layout can
reduce digital feedthrough and crosstalk. At the device
level, a 0.1µF capacitor is required for the VDD, VSS,
and VL_ pins. They should be placed as close to the
pins as possible. More substantial decoupling at the
board level is recommended and is dependent on the
number of devices on the board (Figure 7).
The MAX5631/MAX5632/MAX5633 have three separate
+5V logic power supplies, VLDAC, VLOGIC, and VLSHA.
VLDAC powers the 16-bit digital-to-analog converter,
VLSHA powers the control logic of the SHA array, and
VLOGIC powers the serial interface, sequencer, internal
clock and SRAM. Additional filtering of VLDAC and
VLSHA improves the overall performance of the device.
Chip Information
TRANSISTOR COUNT: 16,229
PROCESS: BiCMOS
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
______________________________________________________________________________________
13


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