MAX5631_06 datasheet(12/16 Pages) MAXIM | 16-Bit DACs with 32-Channel Sample-and-Hold Outputs

Part No.	MAX5631

Description	16-Bit DACs with 32-Channel Sample-and-Hold Outputs

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Manufacturer	MAXIM [Maxim Integrated Products]

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The operating modes can also be selected externally

through CLKSEL and IMMED. In the case where the

control bit in the serial word and the external signal

conflict, the signal that is a logic “1” is dominant.

Modes of Operation

The MAX5631/MAX5632/MAX5633 feature three modes

of operation:

1) Sequence Mode

2) Immediate Update Mode

3) Burst Mode

Sequence Mode

Sequence mode is the default operating mode. The

internal sequencer continuously scrolls through the

SRAM, updating each of the 32 SHAs. At each SRAM

address location, the stored 16-bit DAC code is loaded

to the DAC. Once settled, the DAC output is acquired

by the corresponding SHA. Using the internal

sequencer clock, the process typically takes 320µs to

update all 32 SHAs (10µs per channel). Using an exter-

nal sequencer clock the update process takes 128

clock cycles (four clock cycles per channel).

Immediate Update Mode

Immediate update mode is used to change the con-

tents of a single SRAM location, and update the corre-

sponding SHA output. In Immediate Update Mode, the

selected output is updated before the sequencer

resumes operation. Select Immediate Update Mode by

driving either IMMED or C1 high.

The sequencer is interrupted when

CS is taken low. The

input word is then stored in the proper SRAM address.

The DAC conversion and SHA sample in progress are

completed transparent to the serial bus activity. The

SRAM location of the addressed channel is then modi-

fied with the new data. The DAC and SHA are updated

with the new voltage. The sequencer then resumes

scrolling at the interrupted SRAM address.

This operation can take up to two cycles of the 10µs

sequencer clock. Up to one cycle is needed to allow the

sequencer to complete the operation in progress before

it is freed to update the new channel. An additional

cycle is required to read the new data from memory,

update the DAC, and strobe the sample-and-hold. The

sequencer resumes scrolling from the location at which

it was interrupted. Normal sequencing is suppressed

while loading data, thus preventing other channels from

being refreshed. Under conditions of extremely frequent

Immediate Updates (i.e., 1000 successive updates), this

can result in unacceptable droop.

Figure 5 shows an example of an immediate update

operation. In this example, data for channel 20 is

loaded while channel 7 is being refreshed. The

sequencer operation is interrupted, and no other chan-

nels are refreshed as long as

CS is held low. Once CS

returns high, and the remainder of an fSEQ period (if

any) has expired, channel 20 is updated to the new

data. Once channel 20 has been updated, the

16-Bit DACs with 32-Channel

Sample-and-Hold Outputs

12

______________________________________________________________________________________

7

12

3

SKIP

20

7

8

9

24-BIT

WORD

CS

DIN

CHANNEL 20

UPDATED

INTERRUPTED

CHANNEL REFRESHED

1/fSEQ

LOAD ADDRESS 20

SHA ARRAY

UPDATE

SEQUENCE

Figure 5. Immediate Update Mode Timing Example

SKIP

6

7

SKIP

7

8

5

6

CS

DIN

33 CYCLES TO UPDATE

ALL CHANNELS

1/fSEQ

LOAD MULTIPLE

ADDRESSES

SHA ARRAY

UPDATE

SEQUENCE

7

Figure 6. Burst Mode Timing Example

UPDATE MODE

UPDATE TIME

Immediate Update Mode

2/fSEQ

Burst Mode

33/fSEQ

Table 3. Update Mode

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