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MAX5631 Datasheet(PDF) 10 Page - Maxim Integrated Products

Part No. MAX5631
Description  16-Bit DACs with 32-Channel Sample-and-Hold Outputs
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5631 Datasheet(HTML) 10 Page - Maxim Integrated Products

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16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
10
______________________________________________________________________________________
voltage at the ground-sense input. With a 2.5V refer-
ence, the nominal endpoints are -4.0535V and
+9.0535V (Table 1). Note that these are “virtual” inter-
nal endpoint voltages and cannot be reached with all
combinations of negative and positive power-supply
voltages. The nominal, useable DAC endpoint codes
for the selected power supplies may be calculated as:
lower endpoint code = 32768 - ((2.5V - (VSS + 0.75) /
200µV) (result
≥ 0)
upper endpoint code = 32768 + ((VDD - 2.4 - 2.5V) /
200µV) (result
≤ 65535)
The resistive voltage-divider formed by the output resis-
tor (RO) and the load impedance (RL), scales the out-
put voltage. Determine VOUT_ as follows:
Ground Sense
The MAX5631/MAX5632/MAX5633 include a ground-
sense input (GS), which allows the output voltages to
be referenced to a remote ground. The voltage at GS is
added to the output voltage with unity gain. Note that
the resulting output voltage must be within the valid
output voltage range set by the power supplies.
Output Clamp
The MAX5631/MAX5632/MAX5633 clamps the output
between two externally applied voltages. Internal
diodes at each channel restrict the output voltage to:
The clamping diodes allow the MAX5631/MAX5632/
MAX5633 to drive devices with restricted input ranges.
The diodes also allow the outputs to be clamped during
power-up or fault conditions. To disable output clamp-
ing, connect CH to VDD and CL to VSS, setting the
clamping voltages beyond the maximum output voltage
range.
Serial Interface
The MAX5631/MAX5632/MAX5633 are controlled by an
SPI, QSPI, and MICROWIRE-compatible 3-wire inter-
face. Serial data is clocked into the 24-bit shift register
in an MSB-first format, with the 16-bit DAC data pre-
ceding the 5-bit SRAM address, 2-bit control, and a fill
0 (Figure 4). The input word is framed by
CS. The first
VV
V
V
V
CH
OUT
CL
+
()≥≥()
07
07
..
_
Scaling Factor
R
RR
V
V
scaling factor
L
LO
OUT
CHOLD
=
+
_
DATA
ADDRESS
CONTROL
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01
D0
A4
A3
A2
A1
A0
C1
C0
0
MSB
LSB
Figure 4. Input Word Sequence
Figure 3. Analog Block Diagram
GS
DAC
DATA
CH
OUT_
GAIN
AND
OFFSET
CHOLD
VREF
RO
ONE OF 32 SHA CHANNELS
16-BIT
DAC
RL
CL
AV = 1


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