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M48Z129Y Datasheet(PDF) 3 Page - STMicroelectronics

Part No. M48Z129Y
Description  3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M48Z129Y Datasheet(HTML) 3 Page - STMicroelectronics

 
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M48Z129Y, M48Z129V
WRITE MODE
The M48Z129Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are active.
The start of a write is referenced from the latter oc-
curring falling edge of W or E. A write is terminat-
ed by the earlier rising edge of W or E. The
addresses must be held valid throughout the cycle.
E or W must return high for a minimum of tEHAX
from Chip Enable or tWHAX from Write Enable prior
to the initiation of another read or write cycle.
Data-in must be valid tDVWH prior to the end of
write and remain valid for tWHDX afterward. G
should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W
will disable the outputs tWLQZ after W falls.
DATA RETENTION MODE
With valid VCC applied, the M48Z129Y/V operates
as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automati-
cally deselect, write protecting itself when VCC
falls between VPFD (max), VPFD (min) window. All
outputs become high impedance and all inputs are
treated as “don’t care”.
Table 3. Operating Modes (1)
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Mode
VCC
E
G
W
DQ0-DQ7
Power
Deselect
4.5V to 5.5V
(M48Z129Y)
or
3.0V to 3.6V
(M48Z129V)
VIH
X
X
High Z
Standby
Write
VIL
X
VIL
DIN
Active
Read
VIL
VIL
VIH
DOUT
Active
Read
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min)
(2)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO (2)
X
X
X
High Z
Battery Back-up Mode
Figure 3. Block Diagram
AI03608
RST
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
131,072 x 8
SRAM ARRAY
A0-A16
DQ0-DQ7
E
W
G
POWER
VCC
BL
E
INTERNAL
BATTERY


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