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TMS320F2810 Datasheet(PDF) 81 Page - Texas Instruments |
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TMS320F2810 Datasheet(HTML) 81 Page - Texas Instruments |
81 / 173 page Peripherals 81 April 2001 − Revised July 2007 SPRS174O 4.7 Serial Peripheral Interface (SPI) Module The F281x and C281x devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The SPI module features include: • Four external pins: − SPISOMI: SPI slave-output/master-input pin − SPISIMO: SPI slave-input/master-output pin − SPISTE: SPI slave transmit-enable pin − SPICLK: SPI serial-clock pin NOTE: All four pins can be used as GPIO, if the SPI module is not used. • Two operational modes: master and slave • Baud rate: 125 different programmable rates − Baud rate = LSPCLK (SPIBRR ) 1) , when SPIBRR ≠ 0 = LSPCLK 4 , when SPIBRR = 0, 1, 2, 3 Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum. • Data word length: one to sixteen data bits • Four clocking schemes (controlled by clock polarity and clock phase bits) include: − Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. − Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. − Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. − Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. • Simultaneous receive and transmit operation (transmit function can be disabled in software) • Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. • Nine SPI module control registers: Located in control register frame beginning at address 7040h. NOTE: All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7 −0), and the upper byte (15 −8) is read as zeros. Writing to the upper byte has no effect. Enhanced feature: • 16-level transmit/receive FIFO • Delayed transmit control |
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Similar Description - TMS320F2810_08 |
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