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TMS320F2810 Datasheet(PDF) 7 Page - Texas Instruments

Part No. TMS320F2810
Description  Digital Signal Processors
Download  173 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F2810 Datasheet(HTML) 7 Page - Texas Instruments

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Figures
7
April 2001 − Revised July 2007
SPRS174O
Figure 6−13. Warm Reset in Microcomputer Mode
107
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Figure 6−14. Effect of Writing Into PLLCR Register
108
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Figure 6−15. IDLE Entry and Exit Timing
109
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Figure 6−16. STANDBY Entry and Exit Timing
110
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Figure 6−17. HALT Wakeup Using XNMI
111
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Figure 6−18. PWM Output Timing
112
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Figure 6−19. TDIRx Timing
112
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Figure 6−20. EVASOC Timing
113
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Figure 6−21. EVBSOC Timing
113
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Figure 6−22. External Interrupt Timing
115
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Figure 6−23. General-Purpose Output Timing
115
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Figure 6−24. GPIO Input Qualifier − Example Diagram for QUALPRD = 1
116
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Figure 6−25. General-Purpose Input Timing
116
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Figure 6−26. SPI Master Mode External Timing (Clock Phase = 0)
118
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Figure 6−27. SPI Master External Timing (Clock Phase = 1)
120
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Figure 6−28. SPI Slave Mode External Timing (Clock Phase = 0)
122
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Figure 6−29. SPI Slave Mode External Timing (Clock Phase = 1)
124
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Figure 6−30. Relationship Between XTIMCLK and SYSCLKOUT
127
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Figure 6−31. Example Read Access
129
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Figure 6−32. Example Write Access
130
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Figure 6−33. Example Read With Synchronous XREADY Access
132
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Figure 6−34. Example Read With Asynchronous XREADY Access
133
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Figure 6−35. Write With Synchronous XREADY Access
135
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Figure 6−36. Write With Asynchronous XREADY Access
136
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Figure 6−37. External Interface Hold Waveform
138
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Figure 6−38. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
139
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Figure 6−39. ADC Analog Input Impedance Model
143
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Figure 6−40. ADC Power-Up Control Bit Timing
143
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Figure 6−41. Sequential Sampling Mode (Single-Channel) Timing
145
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Figure 6−42. Simultaneous Sampling Mode Timing
146
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Figure 6−43. McBSP Receive Timing
150
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Figure 6−44. McBSP Transmit Timing
150
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Figure 6−45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
151
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Figure 6−46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
152
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Figure 6−47. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
153
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Figure 6−48. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
154
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