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TMS320F2810 Datasheet(PDF) 47 Page - Texas Instruments |
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TMS320F2810 Datasheet(HTML) 47 Page - Texas Instruments |
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47 / 173 page  Functional Overview 47 April 2001 − Revised July 2007 SPRS174O INT12 MUX INT11 INT2 INT1 CPU (Enable) (Flag) INTx INTx.8 PIEIERx(8:1) PIEIFRx(8:1) MUX INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 From Peripherals or External Interrupts (Enable) (Flag) IER(12:1) IFR(12:1) Global Enable INTM 1 0 PIEACKx (Enable/Flag) Figure 3−7. Multiplexing of Interrupts Using the PIE Block Table 3−12. PIE Peripheral Interrupts† CPU PIE INTERRUPTS CPU INTERRUPTS INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 INT1 WAKEINT (LPM/WD) TINT0 (TIMER 0) ADCINT (ADC) XINT2 XINT1 Reserved PDPINTB (EV-B) PDPINTA (EV-A) INT2 Reserved T1OFINT (EV-A) T1UFINT (EV-A) T1CINT (EV-A) T1PINT (EV-A) CMP3INT (EV-A) CMP2INT (EV-A) CMP1INT (EV-A) INT3 Reserved CAPINT3 (EV-A) CAPINT2 (EV-A) CAPINT1 (EV-A) T2OFINT (EV-A) T2UFINT (EV-A) T2CINT (EV-A) T2PINT (EV-A) INT4 Reserved T3OFINT (EV-B) T3UFINT (EV-B) T3CINT (EV-B) T3PINT (EV-B) CMP6INT (EV-B) CMP5INT (EV-B) CMP4INT (EV-B) INT5 Reserved CAPINT6 (EV-B) CAPINT5 (EV-B) CAPINT4 (EV-B) T4OFINT (EV-B) T4UFINT (EV-B) T4CINT (EV-B) T4PINT (EV-B) INT6 Reserved Reserved MXINT (McBSP) MRINT (McBSP) Reserved Reserved SPITXINTA (SPI) SPIRXINTA (SPI) INT7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT9 Reserved Reserved ECAN1INT (CAN) ECAN0INT (CAN) SCITXINTB (SCI-B) SCIRXINTB (SCI-B) SCITXINTA (SCI-A) SCIRXINTA (SCI-A) INT10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT12 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved † Out of the 96 possible interrupts, 45 interrupts are currently used. The remaining interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts: 1) No peripheral within the group is asserting interrupts. 2) No peripheral interrupts are assigned to the group (example PIE group 12). |
Similar Part No. - TMS320F2810_08 |
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Similar Description - TMS320F2810_08 |
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