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DS4422N+TR Datasheet(PDF) 7 Page - Maxim Integrated Products |
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DS4422N+TR Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 10 page Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC _______________________________________________________________________________________ 7 Example: RFS0 = 80k Ω and register 0xF8h is written to a value of 0xAAh. Calculate the output current. IFS = (0.976V/80k Ω) x (127/16) = 96.838µA The MSB of the output register is 1, so the output is sourcing the value corresponding to position 2Ah (42 decimal). The magnitude of the output current is equal to: 96.838µA x (42/127) = 32.025µA I2C Serial Interface Description I2C Definitions The following terminology is commonly used to describe I2C data transfers: I2C Slave Address: The slave address of the DS4422/DS4424 is determined by the state of the A0 and A1 pins (see Table 1). Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave Devices: Slave devices send and receive data at the master’s request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initi- ates a low-power mode for slave devices. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See Figure 1 for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 1 for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data trans- fer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a spe- cific memory address to begin a data transfer. A repeat- ed START condition is issued identically to a normal START condition. See Figure 1 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL, plus the setup and hold time requirements (Figure 1). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (Figure 1) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock puls- es, including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledge- ment (ACK) or Not Acknowledge (NACK) is always the ninth bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmit- ting a zero during the ninth bit. A device performs a Figure 1. I2C Timing Diagram SDA SCL tHD:STA tLOW tHIGH tR tF tBUF tHD:DAT tSU:DAT REPEATED START tSU:STA tHD:STA tSU:STO tSP STOP NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). START |
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