M36WT864TF datasheet(17/92 Pages) STMICROELECTRONICS

Part #	M36WT864TF

Description	64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product

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M36WT864TF, M36WT864BF

COMMAND INTERFACE - STANDARD COMMANDS

The following commands are the basic commands

used to read, write to and configure the device.

Refer to Table 5, Standard Commands, in con-

junction with the following text descriptions.

Read Array Command

The Read Array command returns the addressed

bank to Read Array mode. One Bus Write cycle is

required to issue the Read Array command and re-

turn the addressed bank to Read Array mode.

Subsequent read operations will read the ad-

dressed location and output the data. A Read Ar-

ray command can be issued in one bank while

programming or erasing in another bank. However

if a Read Array command is issued to a bank cur-

rently executing a Program or Erase operation the

command will be executed but the output data is

not guaranteed.

Read Status Register Command

The Status Register indicates when a Program or

Erase operation is complete and the success or

failure of operation itself. Issue a Read Status

Register command to read the Status Register

content. The Read Status Register command can

be issued at any time, even during Program or

Erase operations.

The following read operations output the content

of the Status Register of the addressed bank. The

Status Register is latched on the falling edge of E

or G signals, and can be read until E or G returns

to VIH. Either E or G must be toggled to update the

latched data. See Table 8 for the description of the

Status Register Bits. This mode supports asyn-

chronous or single synchronous reads only.

Read Electronic Signature Command

The Read Electronic Signature command reads

the Manufacturer and Device Codes, the Block

Locking Status, the Protection Register, and the

Configuration Register.

The Read Electronic Signature command consists

of one write cycle to an address within one of the

banks. A subsequent Read operation in the same

bank will output the Manufacturer Code, the De-

vice Code, the protection Status of the blocks in

the targeted bank, the Protection Register, or the

Configuration Register (see Table 6).

If a Read Electronic Signature command is issued

in a bank that is executing a Program or Erase op-

eration the bank will go into Read Electronic Sig-

nature mode, subsequent Bus Read cycles will

output the Electronic Signature data and the Pro-

gram/Erase controller will continue to program or

erase in the background. This mode supports

asynchronous or single synchronous reads only, it

does not support page mode or synchronous burst

reads.

Read CFI Query Command

The Read CFI Query command is used to read

data from the Common Flash Interface (CFI). The

Read CFI Query Command consists of one Bus

Write cycle, to an address within one of the banks.

Once the command is issued subsequent Bus

Read operations in the same bank read from the

Common Flash Interface.

If a Read CFI Query command is issued in a bank

that is executing a Program or Erase operation the

bank will go into Read CFI Query mode, subse-

quent Bus Read cycles will output the CFI data

and the Program/Erase controller will continue to

Program or Erase in the background. This mode

supports asynchronous or single synchronous

reads only, it does not support page mode or syn-

chronous burst reads.

The status of the other banks is not affected by the

command (see Table 11). After issuing a Read

CFI Query command, a Read Array command

should be issued to the addressed bank to return

the bank to Read Array mode.

See Appendix C, Common Flash Interface, Tables

34, 35, 36, 37, 38, 40, 41, 42 and 43 for details on

the information contained in the Common Flash In-

terface memory area.

Clear Status Register Command

The Clear Status Register command can be used

to reset (set to ‘0’) error bits 1, 3, 4 and 5 in the Sta-

tus Register. One bus write cycle is required to is-

sue the Clear Status Register command. After the

Clear Status Register command the bank returns

to read mode.

The error bits in the Status Register do not auto-

matically return to ‘0’ when a new command is is-

sued. The error bits in the Status Register should

be cleared before attempting a new Program or

Erase command.

Block Erase Command

The Block Erase command can be used to erase

a block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost. If the

block is protected then the Erase operation will

abort, the data in the block will not be changed and

the Status Register will output the error. The Block

Erase command can be issued at any moment, re-

gardless of whether the block has been pro-

grammed or not.

Two Bus Write cycles are required to issue the

command.

s

The first bus cycle sets up the Erase command.

s

The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

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