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09/04/07
IS-5114
3. Device I/O
The IS-5114 has 230 I/O signals, 46 digital power/grounds, and 4 analog power/grounds. All dig-
ital signal pads have 3.3V TTL-compatible output drivers and CMOS inputs, except for SWI,
SWO, and INT[1:0], which have 1.8V TTL-compatible output drivers and CMOS inputs, the crys-
tal and PLL signals, which also run at 1.8V, and the DDR SDRAM Interface, which has SSTL_2
(2.5V) drivers. Table 3-1 provides a description of the I/Os. A package pin map is provided in
“Packaging Information” on page 14.
Note that some pins have more than one possible function. For example, the IDE Controller chip
selects are shared with the Static Memory Controller (SMC) chip select pins (NCS[1:0]). The
pin_sel register is used to control the function of the multi-purpose pins.
3.1
I/O Table Definitions
• I = input, O = output, T = tri-state output, B = bi-directional
• H = logic high, L = logic low
• pd = pad includes a pull-down resistor
• st = pad has Schmitt-triggered input
• * = pad has a drive strength customized for its application
Table 3-1.
I/O Signal Descriptions
Pin Name
Direction
Drive
Strength
Reset
State
Function
DDR SDRAM Interface (All pads are SSTL_2 compatible)
CK
T
*
H
SDRAM clock
CKN
T
*
L
SDRAM clock inverted (clocks are differential)
CKE
T
*
L
Clock enable
CS
T
*
H
Chip select (active low)
RAS
T
*
H
Row address select (active low)
CAS
T
*
H
Column address select (active low)
WE
T
*
H
Write enable (active low)
LDM
T
*
L
Input data mask, lower byte
UDM
T
*
L
Input data mask, upper byte
BA[1:0]
T
*
all bits L
Bank address
MA[13:0]
T
*
all bits L
Memory address
DQ[15:0]
B
*
Input
Data
LDQS
B
*
Input
Data strobe, lower byte
UDQS
B
*
Input
Data strobe, upper byte
VREFS
I
N/A
Input
Reference voltage for SSTL_2 pads (analog, 1.25V nominal)
Imager Interface
PXCLK
I
N/A
Input
Pixel clock
VD
B
2 mA
Input
Vertical synchronization
HD
B
2 mA
Input
Horizontal synchronization
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