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M29W800AT Datasheet(PDF) 3 Page - STMicroelectronics

Part No. M29W800AT
Description  8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash Memory
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M29W800AT Datasheet(HTML) 3 Page - STMicroelectronics

 
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M29W800AT, M29W800AB
Figure 4. LFBGA Connections (Top view through package)
AI00656
D
E
F
8
7
6
5
4
3
2
1
B
C
A
VSS
DQ15
A–1
A15
A14
A12
A13
DQ3
DQ11
DQ10
A18
DU
RB
DQ1
DQ9
DQ8
DQ0
A6
A17
A7
G
E
A0
A4
A3
DQ2
DQ6
DQ13
DQ14
A10
A8
A9
DQ4
VCC
DQ12
DQ5
DU
DU
RP
W
A11
DQ7
A1
A2
VSS
A5
DU
A16
BYTE
Memory Blocks
The devices feature asymmetrically blocked archi-
tecture providing system memory integration. Both
M29W800AT and M29W800AB devices have an
array of 19 blocks, one Boot Block of 16 KBytes or
8 KWords, two Parameter Blocks of 8 KBytes or 4
KWords, one Main Block of 32 KBytes or 16
KWords and fifteen Main Blocks of 64 KBytes or
32 KWords. The M29W800AT has the Boot Block
at the top of the memory address space and the
M29W800AB locates the Boot Block starting at the
bottom. The memory maps are showed in Figure
5.
Each block can be erased separately, any combi-
nation of blocks can be specified for multi-block
erase or the entire chip may be erased. The Erase
operations are managed automatically by the P/
E.C. The block erase operation can be suspended
in order to read from or program to any block not
being erased, and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
Organisation
The M29W800A is organised as 1M x8 or 512K
x16 bits selectable by the BYTE signal. When
BYTE is Low the Byte-wide x8 organisation is se-
lected and the address lines are DQ15A–1 and
A0-A18. The Data Input/Output signal DQ15A–1
acts as address line A–1 which selects the lower
or upper Byte of the memory word for output on
DQ0-DQ7, DQ8-DQ14 remain at High impedance.
When BYTE is High the memory uses the address
inputs A0-A18 and the Data Input/Outputs DQ0-
DQ15. Memory control is provided by Chip Enable
E, Output Enable G and Write Enable W inputs.
A Reset/Block Temporary Unprotection RP tri-lev-
el input provides a hardware reset when pulled
Low, and when held High (at VID) temporarily un-
protects blocks previously protected allowing them
to be programed and erased. Erase and Program
operations are controlled by an internal Program/
Erase Controller (P/E.C.). Status Register data
output on DQ7 provides a Data Polling signal, and
DQ6 and DQ2 provide Toggle signals to indicate
the state of the P/E.C operations. A Ready/Busy
RB output indicates the completion of the internal
algorithms.


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