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M29W800AT Datasheet(PDF) 17 Page - STMicroelectronics

Part No. M29W800AT
Description  8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash Memory
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M29W800AT Datasheet(HTML) 17 Page - STMicroelectronics

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M29W800AT, M29W800AB
Table 17. Write AC Characteristics, W Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Note: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Symbol
Alt
Parameter
M29W800AT / M29W800AB
Unit
80
90
VCC = 3.0V to 3.6V
CL = 30pF
VCC = 3.0V to 3.6V
CL = 30pF
Min
Max
Min
Max
tAVAV
tWC
Address Valid to Next Address Valid
80
90
ns
tAVWL
tAS
Address Valid to Write Enable Low
0
0
ns
tDVWH
tDS
Input Valid to Write Enable High
35
45
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
0
0
ns
tGHWL
Output Enable High to Write Enable Low
0
0
ns
tPHPHH
(1, 2)
tVIDR
RP Rise Time to VID
500
500
ns
tPHWL
(1)
tRSP
RP High to Write Enable Low
4
4
µs
tPLPX
tRP
RP Pulse Width
500
500
ns
tVCHEL
tVCS
VCC High to Chip Enable Low
50
50
µs
tWHDX
tDH
Write Enable High to Input Transition
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
0
0
ns
tWHGL
tOEH
Write Enable High to Output Enable Low
0
0
ns
tWHRL
(1)
tBUSY
Program Erase Valid to RB Delay
90
90
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
30
30
ns
tWLAX
tAH
Write Enable Low to Address Transition
45
45
ns
tWLWH
tWP
Write Enable Low to Write Enable High
35
35
ns
Block Erase (BE) Instruction. This
instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address AAAh
in the Byte-wide configuration or address 555h in
the Word-wide configuration on third cycle after
the two Coded cycles. The Block Erase Confirm
command 30h is similarly written on the sixth cycle
after another two Coded cycles. During the input of
the second command an address within the block
to be erased is given and latched into the memory.
Additional block Erase Confirm commands and
block addresses can be written subsequently to
erase other blocks in parallel, without further Cod-
ed cycles. The erase will start after the erase tim-
eout period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for oth-
er blocks must be given within this delay. The input
of a new Erase Confirm command will restart the
timeout period. The status of the internal timer can
be monitored through the level of DQ3, if DQ3 is ’0’
the Block Erase Command has been given and
the timeout is running, if DQ3 is ’1’, the timeout has
expired and the P/E.C. is erasing the Block(s). If
the second command given is not an erase con-
firm or if the Coded cycles are wrong, the instruc-
tion aborts, and the device is reset to Read Array.
It is not necessary to program the block with 00h
as the P/E.C. will do this automatically before to
erasing to FFh. Read operations after the sixth ris-
ing edge of W or E output the status register status
bits.


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