PX1011BI-EL1G datasheet(7/30 Pages) NXP

Part #	PX1011BI-EL1G

Description	PCI Express stand-alone X1 PHY

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Manufacturer	NXP [NXP Semiconductors]

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7 / 30 page

PX1011B_2

Product data sheet

Rev. 02 — 19 March 2008

7 of 30

NXP Semiconductors

PX1011B

PCI Express stand-alone X1 PHY

Table 8.

PXPIPE interface status signals

Symbol

Type

Signaling

Description

RXVALID

C8

output

SSTL_2

indicates symbol lock and valid data on

RX_DATA and RX_DATAK

PHYSTATUS

D8

output

SSTL_2

used to communicate completion of several PHY

functions including power management state

transitions and receiver detection

RXIDLE

A2

output

SSTL_2

indicates receiver detection of an electrical idle;

this is an asynchronous signal

RXSTATUS0

A9

output

SSTL_2

encodes receiver status and error codes for the

received data stream and receiver detection (see

Table 14)

RXSTATUS1

B9

output

SSTL_2

RXSTATUS2

C9

output

SSTL_2

Table 9.

Clock and reference signals

Symbol

Type

Signaling

Description

TXCLK

J8

input

SSTL_2

source synchronous 250 MHz transmit clock

input from MAC. All input data and signals to the

PHY are synchronized to this clock.

RXCLK

A8

output

SSTL_2

source synchronous 250 MHz clock output for

received data and status signals bound for the

MAC.

REFCLK_P

B1

input

PCIe I/O

100 MHz reference clock input. This is the

spread spectrum source clock for PCI Express.

Differential pair input with 50

Ω on-chip

termination.

REFCLK_N

C1

input

PCIe I/O

PVT

D6

-

analog I/O

input or output to create a compensation signal

internally that will adjust the I/O pads

characteristics as PVT drifts. Connect to VDD

through a 49.9

Ω resistor.

VREFS

J2

input

reference voltage input for SSTL_2 class I

signaling. Connect to 1.25 V.

Table 10.

3.3 V JTAG signals

Symbol

Type

Signaling

Description

TMS

E4

input

3.3 V CMOS

test mode select input

TRST_N

F4

input

3.3 V CMOS

test reset input for the JTAG interface;

active LOW

TCK

F3

input

3.3 V CMOS

test clock input for the JTAG interface

TDI

G3

input

3.3 V CMOS

test data input

TDO

H3

output

3.3 V CMOS

test data output

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