PX1011B_2

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 02 — 19 March 2008

10 of 30

NXP Semiconductors

PX1011B

PCI Express stand-alone X1 PHY

8.5 Power management

The power management signals allow the PHY to manage power consumption. The PHY

meets all timing constraints provided in the PCI Express base specification regarding

clock recovery and link training for the various power states.

Four power states are defined: P0, P0s, P1 and P2. P0 state is the normal operational

state for the PHY. When directed from P0 to a lower power state, the PHY can

immediately take whatever power saving measures are appropriate.

In states P0, P0s and P1, the PHY keeps internal clocks operational. For all state

transitions between these three states, the PHY indicates successful transition into the

designated power state by a single cycle assertion of PHYSTATUS. For all power state

transitions, the MAC must not begin any operational sequences or further power state

transitions until the PHY has indicated that the initial state transition is completed. TXIDLE

should be asserted while in power states P0s and P1.

PHY transmits and receives PCI Express signaling. P0 is the appropriate PHY power

management state for most states in the Link Training and Status State Machine

(LTSSM). Exceptions are listed for each lower power PHY state (P0s, P1 and P2).

idle.

While the PHY is in either P0 or P0s power states, if the receiver is detecting an electrical

idle, the receiver portion of the PHY can take appropriate power saving measures. Note

that the PHY is capable of obtaining bit and symbol lock within the PHY-specified time

(N_FTS with or without common clock) upon resumption of signaling on the receive

channel. This requirement only applies if the receiver had previously been bit and symbol

locked while in P0 or P0s states.

PHY to this state only when both transmit and receive channels are idle. The PHY

indicates a successful entry into P1 (by asserting PHYSTATUS). P1 should be used

for the disabled state, all detect states, and L1.idle state of the Link Training and

Status State Machine (LTSSM).

Fig 4.

Reset

002aac172

RXCLK

RESET_N

PHYSTATUS

100 MHz

250 MHz