8

Specifications ispGDX Family

External Timing Parameters

Over Recommended Operating Conditions

ns

ns

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

–

–

111

4.0

4.0

0.0

–

–

–

–

–

–

–

3.5

3.5

–

10.0

–

–

5.0

6.5

–

–

–

–

5

8.5

6.0

9.5

6.0

6.0

9.0

9.0

–

–

14.0

–

5.0

0.5

–

–

80.0

5.5

5.5

0.0

–

–

–

–

–

–

–

5.0

5.0

–

14.0

–

–

7.0

9.0

–

–

–

–

7.0

11.0

9.0

13.0

8.5

8.5

12.0

12.0

–

–

18.0

–

7.0

0.5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A

A

–

–

–

–

A

A

A

A

B

C

B

C

–

–

–

–

A

A

Data Propagation Delay from any I/O pin to any I/O pin

Data Propagation Delay from MUXsel Inputs to any Output

Clock Frequency with External Feedback

Input Latch or Register Setup Time before any Clk

Output Latch or Register MUX Data Setup Time before any Clk

Latch or Register Hold Time after any Clk

Output Latch or Register Clk (from Y

Input Latch or Register Clk (from Y

Output Latch or Register Clk (from I/O pin) to Output Delay

Input Latch or Register Clock (from I/O pin) to Output Delay

Input to Output Enable

Input to Output Disable

Test OE Output Enable

Test OE Output Disable

Clock Pulse Duration, High

Clock Pulse Duration, Low

Register Reset Delay from RESET Low

Reset pulse width

Output Delay Adder for Output Timings Using Slow Slew Rate

Output Skew (tgco1 across chip)

DESCRIPTION

1

COND.

#

(

)

1

tsu2+tgco1

UNITS

-5

MIN. MAX.

-7

MIN. MAX.

1. All timings measured with one output switching, fast output slew rate setting, except

2

8

010

420

30

4050

6070

I/O Cell Fanout

6

10

4

Maximum

ispGDX timings are specified with a GRP load (fanout) of

four I/O cells. The figure at right shows the Maximum ∆

GRP Delay with increased GRP loads. These deltas

apply to any signal path traversing the GRP (MUXA-D,

OE, CLK, MUXsel0-1). Global Clock signals, which do

not use the GRP, have no fanout delay adder.