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ISPGDX160A-7Q208 Datasheet(PDF) 7 Page - Lattice Semiconductor |
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ISPGDX160A-7Q208 Datasheet(HTML) 7 Page - Lattice Semiconductor |
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7 / 23 page  7 Specifications ispGDX Family Switching Test Conditions Output Load Conditions TEST CONDITION R1 R2 CL A 160Ω 90Ω 35pF B ∞ 90Ω 35pF 160Ω 90Ω 35pF Active High Active Low C 160Ω 90Ω 5pF ∞ 90Ω 5pF Active Low to Z at V +0.5V OL Active High to Z at V -0.5V OH Table 2 - 0004A Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current ispEN Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Quiescent Power Supply Current Dynamic Power Supply Current per Input Switching V V µA µA µA µA mA mA mA/MHz I OL =24 mA I OH =-24 mA 0V ≤ VIN ≤ VIL (MAX.) 3.5V ≤ VIN ≤ VCC 0V ≤ VIN ≤ VIL (MAX.) 0V ≤ VIN ≤ VIL V CC = 5V, VOUT = 0.5V, TA = 25˚C V IL = 0.5V, VIH = VCC One input toggling @ 50% duty cycle, outputs open. VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICCQ ICC – – – – – – – 25 See Note 3 – 2.4 – – – – -100 – – 1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Typical values are at V = 5V and T = 25 oC. 3. I / MHz = (0.0114 x I/O cell fanout) + 0.06 e.g. An input driving four I/O cells at 40 MHz results in a dynamic I of approximately ((0.0114 x 4) + 0.06) x 40 = 4.2 mA. SYMBOL MIN. MAX. TYP.2 PARAMETER CONDITION UNITS 0.55 – -10 10 -150 -150 -250 40 – Input Pulse Levels GND to 3.0V Input Rise and Fall Time ≤ 1.5ns 10% to 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See figure at right 3-state levels are measured 0.5V from steady-state active level. CC A OUT DC Electrical Characteristics Over Recommended Operating Conditions + 5V R1 R2 CL* Device Output Test Point *CL includes Test Fixture and Probe Capacitance. CC CC |
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