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W83195BG-341 Datasheet(PDF) 18 Page - Winbond |
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W83195BG-341 Datasheet(HTML) 18 Page - Winbond |
18 / 26 page W83195BR-341/W83195BG-341 CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET - 14 - 7.16 Register 16: DRAM Buffer Control (1 = Enable, 0 = Disable) (Default: 7Fh) BIT NAME PWD FUNCTION DESCRIPTION 7 Reserve 0 Reserve 6 FBOUT_EN 1 FBOUT output control 5 DDR5 1 DDRT5, DDRC5 / SDRAM10, 11 output control 4 DDR4 1 DDRT4, DDRC4 / SDRAM8, 9 output control 3 DDR3 1 DDRT3, DDRC3 / SDRAM6, 7 output control 2 DDR2 1 DDRT2, DDRC2 / SDRAM4, 5 output control 1 DDR1 1 DDRT1, DDRC1 / SDRAM2, 3 output control 0 DDR0 1 DDRT0, DDRC0 / SDRAM0, 1 output control 7.17 Register 17: Slew Rate Control (Default: CFh) BIT NAME PWD FUNCTION DESCRIPTION 7 FBOUT_S2 1 6 FBOUT_S1 1 FBOUT slew rate control 11: Strong, 00: Weak, 10/01: Normal 5 CPUOD_S2 0 4 CPUOD_S1 0 CPUODT/C slew rate control 11: Strong, 00: Weak, 10/01: Normal 3 DDR3_S2 1 2 DDR3_S1 1 DDR3, 4,5/SDRAM6, 7,8,9,10,11 slew rate control 11: Strong, 00: Weak, 10/01: Normal 1 DDR0_S2 1 0 DDR0_S1 1 DDR0, 1,2/SDRAM 0,1,2,3,4,5 slew rate control 11: Strong, 00: Weak, 10/01: Normal 7.18 Register 18: M/N Time & Type Control (Default: 5Bh) BIT NAME PWD FUNCTION DESCRIPTION 7 N_Time<2> 0 6 N_Time<1> 1 5 N_Time<0> 0 M/N mode N value change time control 4 M_Time<2> 1 3 M_Time<1> 1 2 M_Time<0> 0 M/N mode M value change time control 1 N_TYPE 1 Reserved for Winbond internal use, don’t modify it 0 M_TYPE 1 Reserved for Winbond internal use, don’t modify it Note: This Byte only for Winbond internal and BOIS program use, the release version please reserved this byte. |
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