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W83195BG-341 Datasheet(PDF) 15 Page - Winbond |
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W83195BG-341 Datasheet(HTML) 15 Page - Winbond |
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15 / 26 page  W83195BR-341/W83195BG-341 CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET Publication Release Date: March, 2006 - 11 - Revision 1.1 Table-2 REGISTER 1 /BIT 6 L_MODE REGISTER 9/BIT6 SEL_CLKSTOP PIN 26 PIN8 PIN18 0 0(default) PD# AGP2 PCI6 0 1 PD# PCI_STOP# CLK_STOP# 1 0 RESET# AGP2 PCI6 1 1 RESET# AGP2 PCI6 Table-3 CPU, AGP, PCI divider ratio selection Table DS2~DS0 CPU AGP PCI 000 2 5 10 001 2 6 12 010 3 6 12 011 4 6 12 100 6 6 12 101 3 7 14 110 4 8 16 111 4 10 20 7.10 Register 10: Control (Default: 0Ah) BIT NAME PWD FUNCTION DESCRIPTION 7 EN_MN_PROG 0 0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. 6 N<10> 0 Programmable N divisor value bit 10 5 Reserve 0 4 Reserve 0 Reserved 3 IVAL<3> 1 2 IVAL<2> 0 1 IVAL<1> 1 0 IVAL<0> 0 Charge pump current selection |
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