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M29W004T Datasheet(PDF) 17 Page - STMicroelectronics

Part No. M29W004T
Description  4 Mbit 512Kb x8, Boot Block Low Voltage Single Supply Flash Memory
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M29W004T Datasheet(HTML) 17 Page - STMicroelectronics

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background image
Symbol
Alt
Parameter
M29W004T / M29W004B
Unit
-120
-150
VCC = 2.7V to 3.6V
VCC = 2.7V to 3.6V
Min
Max
Min
Max
tAVAV
tWC
Address Valid to Next Address Valid
120
150
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
50
65
ns
tDVWH
tDS
Input Valid to Write Enable High
50
65
ns
tWHDX
tDH
Write Enable High to Input Transition
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
0
0
ns
tWHWL
tWPH Write Enable High to Write Enable Low
30
35
ns
tAVWL
tAS
Address Valid to Write Enable Low
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
50
65
ns
tGHWL
Output Enable High to Write Enable Low
0
0
ns
tVCHEL
tVCS
VCC High to Chip Enable Low
50
50
µs
tWHGL
tOEH
Write Enable High to Output Enable Low
0
0
ns
tPHPHH
(1,2)
tVIDR RP Rise Time to VID
500
500
ns
tPLPX
tRP
RP Pulse Width
500
500
ns
tWHRL
(1)
tBUSY Program Erase Valid to RB Delay
90
90
ns
tPHWL
(1)
tRSP
RP High to Write Enable Low
4
4
µs
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Table 15B. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70
°C, –20 to 85°C or –40 to 85°C)
after the sixth rising edge of W or E output the
status register status bits.
During the execution of the erase by the P/E.C., the
memory accepts only the Erase Suspend ES and
Read/Reset RD instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle bit DQ2 and
DQ6 toggle during the erase operation. They stop
when erase is completed. After completion the
Status Register bit DQ5 returns ’1’ if there has been
an erase failure. In such a situation, the Toggle bit
DQ2 can be used to determine which block is not
correctly erased. In the case of erase failure, a
Read/Reset RD instruction is necessary in order to
reset the P/E.C.
Chip Erase (CE) Instruction. This instruction uses
six write cycles. The Erase Set-up command 80h
is written to address 5555h on the third cycle after
the two Coded cycles. The Chip Erase Confirm
command 10h is similarly written on the sixth cycle
after another two Coded cycles. If the second
command given is not an erase confirm or if the
Coded cycles are wrong, the instruction aborts and
the device is reset to Read Array. It is not necessary
to program the array with 00h first as the P/E.C. will
automatically do this before erasing it to FFh. Read
operations after the sixth rising edge of W or E
output the Status Register bits. During the execu-
tion of the erase by the P/E.C., Data Polling bit DQ7
returns ’0’, then ’1’ on completion. The Toggle bits
DQ2 and DQ6 toggle during erase operation and
17/30
M29W004T, M29W004B


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