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VND5050JTR-E Datasheet(PDF) 11 Page - STMicroelectronics |
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VND5050JTR-E Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 37 page VND5050J-E / VND5050K-E Electrical specifications 11/37 Symbol Parameter Test conditions Min. Typ. Max. Unit Symbol Parameter Test conditions Min. Typ. Max. Unit Table 10. Openload detection IOL Openload On state detection threshold VIN = 5V ,8V<VCC<18V 10 See Figure 18 70 mA tDOL(on) Openload On state detection delay IOUT = 0A, VCC=13V (see Figure 4) 200 µs tPOL Delay between INPUT falling edge and STATUS rising edge in Openload condition IOUT = 0A (see Figure 4) 200 500 1000 µs VOL Openload Off state voltage detection threshold VIN = 0V, 8V<VCC<16V 2 See Figure 19 4V tDSTKON Output short circuit to VCC detection delay at turn Off (see Figure 4)180 tPOL µs Table 11. Logic input VIL Input low level 0.9 V IIL Low level input current VIN =0.9 V 1 µA VIH Input high level 2.1 V IIH High level input current VIN = 2.1 V 10 µA VI(hyst) Input hysteresis voltage 0.25 V VICL Input clamp voltage IIN = 1mA IIN = -1mA 5.5 -0.7 7V V VSDL STAT_DIS low level voltage 0.9 V ISDL Low level STAT_DIS current VSD = 0.9 V 1 µA VSDH STAT_DIS high level voltage 2.1 V ISDH High level STAT_DIS current VSD = 2.1 V 10 µA VSD(hyst) STAT_DIS hysteresis voltage 0.25 V VSDCL STAT_DIS clamp voltage ISD= 1mA ISD= -1mA 5.5 -0.7 7V V |
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